Electronic apparatus having parallel memory banks

Patent metadata

Field	Value
Publication number	US-2016378650-A1
Application number	US-201615076118-A
Country	US
Kind code	A1
Filing date	Mar 21, 2016
Priority date	Jan 10, 2012
Publication date	Dec 29, 2016
Grant date	—

Abstract

An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.

First claim

1 - 28 . (canceled)

29 . An electronic apparatus comprising:
a processor; and a memory subsystem that includes a plurality of parallel memory banks to store replicas of a look-up table, and to enable reading of at least two look-up values from the look-up table at a same time.

30 . The electronic apparatus of claim 29 , wherein the at least two look-up values are to be stored in at least two of the plurality of parallel memory banks.

31 . The electronic apparatus of claim 30 , wherein each memory bank to include a plurality of look-up table replicas.

32 . The electronic apparatus of claim 29 , wherein the memory subsystem to be provided in a vector lookup access mode.

33 . The electronic apparatus of claim 32 , wherein a vector lookup access to be provided when the memory subsystem is in the vector lookup access mode.

34 . The electronic apparatus of claim 29 , wherein each memory bank to include a plurality of addressable words per bank.

35 . The electronic apparatus of claim 34 , wherein each word to include a plurality of elements for the particular bank.

36 . The electronic apparatus of claim 29 , wherein the processor is a single-instruction-multiple data processor.

37 . The electronic apparatus of claim 29 , wherein the memory subsystem is provided on-chip with the processor.

38 . The electronic apparatus of claim 29 , wherein the processor to perform high dynamic range imaging (HDR).

39 . The electronic apparatus of claim 29 , wherein the processor to perform image enhancement.

40 . The electronic apparatus of claim 29 , wherein the processor to perform object detection and tracking.

41 . An electronic apparatus comprising:
a processor; and a plurality of parallel memory banks to store replicas of a look-up table, and to provide a vector lookup access to at least two look-up values from the look-up table at a same time.

42 . The electronic apparatus of claim 41 , wherein the at least two look-up values are to be stored in at least two of the plurality of parallel memory banks.

43 . The electronic apparatus of claim 42 , wherein each memory bank to include a plurality of look-up table replicas.

44 . The electronic apparatus of claim 41 , wherein the memory subsystem to be provided in a vector lookup access mode.

45 . The electronic apparatus of claim 44 , wherein a vector lookup access to be provided when the memory subsystem is in the vector lookup access mode.

46 . The electronic apparatus of claim 41 , wherein each memory bank to include a plurality of addressable words per bank.

47 . The electronic apparatus of claim 46 , wherein each word to include a plurality of elements for the particular bank.

48 . The electronic apparatus of claim 41 , wherein the processor is a single-instruction-multiple data processor.

49 . The electronic apparatus of claim 41 , wherein the memory subsystem is provided on-chip with the processor.

Assignees

• Intel Corp

Inventors

• Jakovljevic Radomir
• Beric Aleksandar
• Van Dalen Edwin
• Milicev Dragan

Classifications

• G06F9/3004

  to perform operations on memory · CPC title

• G06F15/8007

  single instruction multiple data [SIMD] multiprocessors · CPC title

• G06F12/0207 Primary

  with multidimensional access, e.g. row/column, matrix · CPC title

• G06F12/04 Primary

  Addressing variable-length words or parts of words · CPC title

• G06F5/08 Primary

  having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register {(G06F5/065 takes precedence; shift registers per se G11C19/00)} · CPC title