Software-Initiated Trace Integrated with Hardware Trace

Patent metadata

Field	Value
Publication number	US-2016378636-A1
Application number	US-201514751759-A
Country	US
Kind code	A1
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

In an embodiment, a processor includes a core that is to include fetch logic to fetch instructions that include first instructions and a second instruction. The core also includes execution logic to execute the instructions. The execution logic is to retrieve an operand value that is one of an immediate value, a register value, and a memory value stored in a memory location, responsive to execution of the second instruction. The core also includes logic to output a packet that includes a representation of the operand value responsive to execution of the second instruction. The core also includes processor trace (PT) logic to generate a processor trace that includes a plurality of PT packets, where each PT packet correspond to an outcome of execution of a respective first instruction. The processor trace logic is further to include the packet within the processor trace. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . A processor comprising:
a core to include:
fetch logic to fetch instructions that include first instructions and a second instruction;
execution logic to execute the instructions, wherein the execution logic is to retrieve an operand value that is one of an immediate value, a register value, and a memory value stored in a memory location, responsive to execution of the second instruction;
logic to output a packet that includes a representation of the operand value responsive to execution of the second instruction; and
processor trace (PT) logic to generate a processor trace that includes a plurality of PT packets, wherein each PT packet corresponds to an outcome of execution of a respective first instruction, the processor trace logic further to include the packet within the processor trace.

2 . The processor of claim 1 , wherein the packet is to include an indicator that corresponds to an address of the second instruction.

3 . The processor of claim 1 , wherein the PT logic is to include in the processor trace a first PT packet that includes an indication of a control flow that results from execution of a particular first instruction by the execution logic.

4 . The processor of claim 1 , wherein the PT logic is to include in the processor trace a first PT packet that is to include a data address of output data that results from execution of a particular first instruction by the execution logic.

5 . The processor of claim 1 , further comprising a processor trace cache to store the processor trace generated by the processor trace logic.

6 . The processor of claim 1 , wherein the operand value corresponds to an output of execution of a particular first instruction by the execution logic.

7 . The processor of claim 1 , wherein the logic is to include in the packet a header that is to distinguish the packet from the PT packets.

8 . The processor of claim 1 , wherein the logic is to output a plurality of packets, each packet to correspond to execution of a respective second instruction, and the processor trace logic is to interleave each of the plurality of packets into the processor trace.

9 . A system comprising:
a memory to store a program that includes at least one instruction of a first type and at least one instruction of a second type; and a processor that includes a first core that includes:
execution logic to execute the program and to retrieve a first operand value of a first operand responsive to execution of a first instruction of the second type, wherein the first instruction of the second type specifies the first operand;
logic to output a first packet that includes a representation of the first operand value responsive to execution of the first instruction of the second type; and
processor trace logic to generate, for each instruction of the first type executed, a respective processor trace (PT) packet that corresponds to an outcome of execution of the instruction of the first type, the processor trace logic further to include the first packet in a processor trace that includes each generated PT packet.

10 . The system of claim 9 , wherein the first operand comprises an identifier of a storage location.

11 . The system of claim 9 , wherein the first operand value is to be determined based on execution of a particular instruction of the first type.

12 . The system of claim 9 , wherein the operand specifies an immediate value that is associated with execution of a particular instruction of the first type.

13 . The system of claim 9 , wherein the logic is to include in the first packet an indicator corresponds to an instruction pointer of the first instruction of the second type.

14 . The system of claim 9 , wherein the program is to include a plurality of instructions of the second type, wherein each instruction of the second type has a corresponding identifier, wherein for each instruction of the second type the logic is to output a corresponding packet that is to include the identifier of the corresponding instruction of the second type.

15 . The system of claim 14 , wherein the identifier corresponds to an instruction pointer of the corresponding instruction of the second type.

16 . The system of claim 14 , wherein the processor trace logic is to interleave the packets with the PT packets within the processor trace.

17 . A machine-readable medium having stored thereon data, which if used by at least one machine, cause the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
executing, by a core, instructions that include at least one instruction of a first type and a an instruction of a second type, wherein execution of the instruction of the second type results in output of an operand value that is one of an immediate value, a register value and a memory value stored in a memory location; forming, by logic of the core, a packet that includes the operand value; and including the packet into a processor trace (PT) that is to include at least one PT packet, wherein each PT packet corresponds to an outcome of execution of a corresponding instruction of the first type.

18 . The machine readable medium of claim 17 , wherein the packet is to include a packet header that differentiates the packet from PT packets.

19 . The machine-readable medium of claim 17 , wherein the instruction of the second type has an identifier, and wherein the packet is to include the identifier.

20 . The machine-readable medium of claim 17 , wherein the instructions include a plurality of instructions of the second type, wherein execution of each instruction of the second type is to result in retrieval of a corresponding operand value, and wherein the method further includes for each instruction of the second type executed forming a corresponding packet that includes the corresponding operand value, and interleaving the corresponding packet with a plurality of PT packets into the processor trace.

Assignees

• Intel Corp

Inventors

• Strong Beeman C
• Brandt Jason W
• Lachner Peter
• Kleen Andreas
• Crossland James B
• Opferman Toby

Classifications

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F11/3466 Primary

  Performance evaluation by tracing or monitoring · CPC title

• G06F2201/865

  Monitoring of software · CPC title