Repair of failed firmware through an unmodified dual-role communication port

Patent metadata

Field	Value
Publication number	US-2016378633-A1
Application number	US-201514752937-A
Country	US
Kind code	A1
Filing date	Jun 27, 2015
Priority date	Jun 27, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A repair engine for a computing platform is separate from the repeatedly-rewritten storage components for software and firmware. For example, the repair engine may reside in ROM or hardware logic. Through dedicated connections to one or more controllers, the repair engine detects when any of the platform's dual-role ports (e.g., on-the-go USB ports) is connected to a host device. The repair engine responds by opening firmware-independent communication with the host device and supporting the downloading and execution (DnX) of a firmware image from the host. Because the communication is initiated independently of the firmware, even a catastrophic firmware failure is repairable without requiring a user to identify and use a specially modified port.

First claim

We claim:

1 . A device, comprising:
a plurality of dual-role port receptacles, each connectable to a host device or a peripheral device; a rewritable storage component having sufficient capacity for containing firmware for the device; a non-rewritable logic component coupled to a first controller and to a second controller; a plurality of transmitters and receivers controlled by the second controller and coupled to transmit and receive messages through each of the dual-role port receptacles; and a sensor coupled to each of the dual-role port receptacles and positioned to sense a feature of an inserted connector end, wherein an output of the sensor is transmitted to the first controller; and wherein at least one communication path connecting the dual-role port receptacle, the sensor, the first controller, the non-rewritable logic component, the second controller, and the dual-role port receptacle bypasses the rewritable storage component.

2 . The device of claim 1 , wherein the first controller and the non-rewritable logic component are located on different chips and connected to each other by a bus.

3 . The device of claim 1 , wherein the first controller and the non-rewritable logic component are co-located on a single chip.

4 . The device of claim 1 , wherein the first controller is integrated into a hub connected to the non-rewritable logic component.

5 . The device of claim 1 , wherein the first controller is an embedded controller.

6 . The device of claim 1 , wherein the first controller is an XHCI controller.

7 . The device of claim 1 , further comprising a hub coupled to the non-rewritable logic component.

8 . The device of claim 7 , wherein the hub comprises an integrated sensor hub or a platform controller hub.

9 . The device of claim 7 , wherein the hub comprises a microcontroller or is coupled to a microcontroller.

10 . The device of claim 1 , wherein a power path between a power source, power-delivery and power-management components, the first controller, the non-rewritable logic component, and the second controller bypasses the rewritable storage component.

11 . The device of claim 1 , wherein power is supplied to the first controller, the non-rewritable logic component, and the second controller from a connected host through one of the dual-port receptacles.

12 . The device of claim 1 , wherein at least one pin strap coupled to the non-rewritable logic component identifies a platform configuration of the device.

13 . A system, comprising:
a first computing platform, wherein the first computing platform comprises:
a plurality of dual-role communication ports;
a firmware-storage component; and
a control system comprising:
a sensor coupled to each of the communication ports, wherein the sensor responds to a receptacle connection and responds differently to an upstream-facing connection than to a downstream-facing connection; and
at least one controller coupled to the sensor and to each of the communication ports independently of the firmware-storage component;

a second computing platform, wherein the second computing platform comprises:
a communication port capable of a downstream-facing connection;
a data-storage component containing a clean firmware image operable on the first computing platform; and
a host controller coupled to the communication port and the data-storage component; and
a connector, to connect one of the dual-role ports as an upstream-facing connection to the communication port and carry subsequent messages between the first computing platform and the second computing platform.

14 . The system of claim 13 , wherein the connector has a first end for making an upstream-facing connection and a second end for making a downstream-facing connection;
wherein the first end has a first feature and the second end has a second feature; wherein a receptacle of each of the dual-role communication ports accepts the first end or the second end; and wherein the control system detects the upstream-facing or downstream-facing nature of the connection by detecting the first feature or the second feature.

15 . The system of claim 13 , wherein a difference between the first feature and the second feature comprises a pin.

16 . The system of claim 13 , wherein a difference between the first feature and the second feature comprises a voltage drop between an identifying pin and a reference pin.

17 . The system of claim 13 , wherein the connector comprises a power-delivery path.

18 . The system of claim 13 , wherein part of the control system of the first computing platform consumes power delivered over the power-delivery path.

19 . The system of claim 13 , wherein the connector is a Universal Serial Bus connector comprising a differently connected ID pin on each connector end.

20 . A non-transitory machine-readable information storage medium containing code that, when executed, causes an electronic component to perform actions, the actions comprising:
polling a first controller to determine whether any one of a plurality of communication ports is connected to a host device, and if so, which one; responding to detection of the connected host device by causing a second controller to:
initiate communication with the host device through the connected port;
transmit a “download and execute” request;
receive a firmware image from the connected host device; and
write the firmware image to a non-transitory rewritable storage component;
wherein the non-transitory machine-readable information storage medium is separate from and independent of the non-transitory rewritable storage component; and wherein at least one communication path connecting the plurality of communication ports, the first controller, the non-transitory machine-readable information storage medium, and the second controller bypasses the non-transitory rewritable storage component.

21 . The non-transitory machine-readable information storage medium of claim 20 , wherein the polling of the first controller is triggered by a firmware failure.

22 . The non-transitory machine-readable information storage medium of claim 20 , wherein the non-transitory machine-readable information storage medium comprises non-rewriteable memory.

23 . The non-transitory machine-readable information storage medium of claim 20 , wherein the non-transitory machine-readable information storage medium comprises fixed-function hardware.

24 . The non-transitory machine-readable information storage medium of claim 20 , additionally containing code that, when executed, causes a machine to perform further actions, the actions comprising routing, buffering, backing up, or otherwise assisting the writing of the firmware image to the non-transitory rewritable storage component.

25 . The non-transitory machine-readable information storage medium of claim 20 , additionally containing code that, when executed, causes a machine to perform further actions, the actions comprising selecting one of a plurality of stored processes of polling and responding according to criteria comprising strap-pin settings of a non-rewritable memory component.

Assignees

• Intel Corp

Inventors

• Sarangdhar Nitin V
• Kataria Mukesh
• Nge Chee Lim
• Astekar Basavaraj B
• Vadivelu Karthi R

Classifications

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F11/3051 Primary

  Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247) · CPC title

• G06F11/3027

  where the computing system component is a bus · CPC title

• G06F11/2635

  using a storage for the test inputs, e.g. test ROM, script files · CPC title

• G06F11/302

  where the computing system component is a software system · CPC title