Computing apparatus with real time clock without a battery

Patent metadata

Field	Value
Publication number	US-2016378135-A1
Application number	US-201514750159-A
Country	US
Kind code	A1
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

The present disclosure describes embodiments of apparatuses and methods related to a computing apparatus with a real time clock (RTC) coupled to a bus, where the RTC does not have a backup power source to maintain time and date of the RTC. The computing apparatus may have firmware coupled to the bus, and the firmware may contain boot logic with network time protocol (NTP) logic. The computing apparatus may have persistent memory coupled to the bus with configuration parameters. The computing apparatus may have a controller coupled to the bus, where the controller is to retrieve the configuration parameters from the persistent memory and processes the boot logic with the NTP logic using the configuration parameters to transmit an NTP request over the bus and receives a coordinated universal time (UTC) over the bus and stores the UTC in the RTC.

First claim

What is claimed is:

1 . An apparatus for computing, comprising:
a real time clock (RTC) coupled to a bus and without a battery to maintain time and date of the real time clock; firmware coupled to the bus and to contain boot logic with network time protocol (NTP) logic; persistent memory coupled to the bus and with configuration parameters; and a controller coupled to the bus and to retrieve the configuration parameters from the persistent memory, wherein the controller is to process the boot logic with the NTP logic using the configuration parameters to transmit an NTP request over the bus and to receive a coordinated universal time (UTC) over the bus and to store the UTC in the RTC.

2 . The apparatus of claim 1 , wherein the controller is further to process the boot logic with the NTP logic using the configuration parameters to set parameters of components of the apparatus.

3 . The apparatus of claim 1 , further comprising:
a network port coupled to the bus, wherein the controller is to transmit the NTP request over the network port to a NTP server and to receive over the network port from the NTP server the UTC.

4 . The apparatus of claim 1 , further comprising:
a baseboard management controller (BMC) coupled to the bus, wherein the controller is to transmit the NTP request over the bus to the BMC and the controller is to receive from the BMC the UTC.

5 . The apparatus of claim 1 , wherein the controller comprises a cache memory, and uses the cache memory as random access memory to process the boot logic.

6 . The apparatus of claim 1 , wherein the firmware includes storage logic, wherein the controller is to process the storage logic to store in the persistent memory one or more policies of the apparatus.

7 . The apparatus of claim 6 , wherein the one or more policies include a startup policy that includes boot from a no power status and boot to a full operating system status.

8 . The apparatus of claim 1 , wherein the firmware is in a silicon block of a management engine of the apparatus.

9 . The apparatus of claim 1 , wherein the persistent memory is in a silicon block of a management engine of the apparatus.

10 . The apparatus of claim 1 , wherein the persistent memory is flash memory.

11 . The apparatus of claim 1 , further comprising:
a processor with a general input output pin (GIOP) with a state, wherein the controller is to read the GIOP and to set the boot logic to a default boot logic based on the state of the GIOP.

12 . A method for setting a real time clock of a computing apparatus, comprising:
receiving, by a computing apparatus with a controller, a power input, the computing apparatus unpowered before receiving the power input and having a real time clock (RTC) without a backup battery; retrieving, by the controller, configuration parameters from a persistent memory, by processing boot logic from a firmware block, wherein the boot logic includes network time protocol (NTP) logic; transmitting, by the controller, over a bus coupled to the controller a NTP request in response to processing the boot logic with the NTP logic; receiving, by the controller, over the bus a coordinated universal time (UTC) in response to the NTP request; and storing, by the controller, the UTC response in the RTC in response to processing the NTP logic.

13 . The method of claim 12 , further comprising:
configuring, by the controller, components of the computing apparatus in response to processing the boot logic and the configuration parameters.

14 . The method of claim 12 , further comprising:
storing, by the controller, in the persistent memory one or more policies of the computing apparatus, wherein the one or more polices include a startup policy that includes boot from a no power status and boot to a full operating system status.

15 . The method of claim 12 , wherein the bus is coupled to a network port and the NTP request is transmitted over the bus to the network port to a NTP server, wherein the UTC is received over the bus from the network port from the NTP server.

16 . The method of claim 12 , wherein a baseboard management controller (BMC) is coupled to the bus and the NTP request is transmitted over the bus to the BMC, wherein the UTC is received over the bus from the BMC.

17 . The method of claim 12 , wherein the processing of the boot logic further includes using a cache memory as random access memory.

18 . The method of claim 12 , wherein the firmware is in a silicon block of a management engine of the apparatus.

19 . The method of claim 12 , wherein the persistent memory is in a silicon block of a management engine of the apparatus.

20 . The method of claim 12 , wherein the persistent memory is flash memory.

21 . The method of claim 12 , further comprising:
reading, by the controller, a general input output pin (GIOP) of a processor of the computing apparatus, the GIOP with a state, wherein the controller reads the GIOP and sets the boot logic to a default boot logic based on the state of the GIOP.

22 . One or more non-transitory computer readable media comprising instructions to cause a computing apparatus, in response to execution of the instructions by a processor of the computing apparatus, to:
process a boot logic with network time protocol (NTP) logic from a firmware block when the computing apparatus receives power from a power input, wherein the computing apparatus is unpowered before the computing apparatus receives power from the power input and has a real time clock (RTC) without a backup battery; retrieve configuration parameters from a persistent memory by processing the boot logic with the NTP logic; transmit over a bus a NTP request in response to processing the boot logic with the NTP logic and the configuration parameters; receive over the bus a coordinated universal time (UTC) in response to the NTP request; and store the UTC response in the RTC in response to processing the NTP logic.

23 . The non-transitory computer readable media of claim 22 , further comprising instructions to cause the computing apparatus, in response to execution of the instructions by the processor of the computing apparatus, to:
configure components of the computing apparatus in response to processing the boot logic and the configuration parameters.

24 . The non-transitory computer readable media of claim 22 , wherein the bus is coupled to a network port and the NTP request is transmitted over the bus to the network port to a NTP server, wherein the UTC is received over the bus from the network port from the NTP server.

25 . The non-transitory computer readable media of claim 22 , wherein a baseboard management controller (BMC) is coupled to the bus and the NTP request is transmitted over the bus to the BMC, wherein the UTC is received over the bus from the BMC.

Assignees

• Intel Corp

Inventors

• Larson Thane M
• Krithivas Ramamurthy
• Ruffin Chris

Classifications

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F1/14 Primary

  Time supervision arrangements, e.g. real time clock · CPC title

• G06F9/4406

  Loading of operating system · CPC title