Chip and method for testing a processing component of a chip

Patent metadata

Field	Value
Publication number	US-2016377677-A1
Application number	US-201615191553-A
Country	US
Kind code	A1
Filing date	Jun 24, 2016
Priority date	Jun 24, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

In accordance with one embodiment, a chip is provided which includes an interface configured to receive test data and masking data, a processing component having a plurality of scan chains. Each scan chain is configured to generate a test response on the basis of a processing of the test data. The chip further includes a compression circuit configured to compress the test responses generated by the scan chains to form a compressed test response, and a signature generating circuit configured to generate a signature on the basis of the compressed test response, depending on whether the masking data specify that the compressed test response is to be masked.

First claim

What is claimed is:

1 . A chip, comprising:
an interface configured to receive test data and masking data; a processing component having a plurality of scan chains, wherein each scan chain is configured to generate a test response on the basis of a processing of the test data; a compression circuit configured to compress the test responses generated by the scan chains to form a compressed test response; and a signature generating circuit configured to generate a signature on the basis of the compressed test response, depending on whether the masking data specify that the compressed test response is to be masked.

2 . The chip of claim 1 ,
wherein each scan chain is configured to generate a sequence of test responses on the basis of the processing of the test data; and wherein the compression circuit is configured to compress the sequences of test responses generated by the scan chains to form a sequence of compressed test responses.

3 . The chip of claim 2 ,
wherein the masking data specify which compressed test responses of the sequence of compressed test responses are to be masked; and wherein the signature generating circuit is configured to generate the signature on the basis of the compressed test responses apart from those compressed test responses of the sequence of compressed test responses which are to be masked.

4 . The chip of claim 3 ,
wherein the signature generating circuit is configured to generate the signature on the basis of the compressed test responses which are not to be masked and predefined values for those compressed test responses of the sequence of compressed test responses which are to be masked.

5 . The chip of claim 1 , further comprising:
a masking circuit configured to mask the compressed test response if it is to be masked in accordance with the masking data.

6 . The chip of claim 5 ,
wherein masking a test response comprises overwriting the test response with a predefined value.

7 . The chip of claim 5 ,
wherein the chip has a security mode in which the masking circuit is configured to mask the compressed test response independently of the masking data.

8 . The chip of claim 7 , further comprising:
a security circuit which is configured to deactivate the security mode when a predefined key is input, such that the masking circuit masks the compressed test response depending on the masking data.

9 . The chip of claim 7 , further comprising:
a detection circuit configured to detect whether the security mode is deactivated even though the chip is not in a test mode, and to output an alarm signal if the security mode is deactivated even though the chip is not in a test mode.

10 . The chip of claim 1 ,
wherein the masking circuit is configured to mask predefined compressed test responses of the compressed test responses independently of the masking data.

11 . The chip of claim 1 , further comprising:
a control circuit configured to deactivate the processing of a compressed test response for generating a signature if the compressed test response is to be masked.

12 . The chip of claim 1 ,
wherein each test response is a bit.

13 . The chip of claim 12 ,
wherein compressing the test responses is an XOR combination of the test responses, such that the compressed test response is a test response bit.

14 . The chip of claim 13 ,
wherein the masking data comprise, for each test response bit of a sequence of test response bits, a bit which indicates whether the test response bit is to be masked.

15 . The chip of claim 1 ,
wherein the scan chains are configured to process the test data during a plurality of clock cycles of a clock signal and to output a test response for each clock cycle of the clock signal.

16 . The chip of claim 15 ,
wherein the compression circuit is configured to compress, for each clock cycle of the clock signal, the test responses output by the scan chains for the clock cycle to form a compressed test response.

17 . The chip of claim 1 ,
wherein the interface comprises a pin and is configured to receive the test data and masking data via the pin and to output the signature via the pin.

18 . A method for testing a processing component of a chip, the method comprising:
receiving test data and masking data by the chip; generating, by each scan chain of a plurality of scan chains of the processing component, a test response on the basis of a processing of the test data by the scan chain; compressing the test responses generated by the scan chains to form a compressed test response; and generating a signature on the basis of the compressed test response depending on whether the masking data specify that the compressed test response is to be masked.

19 . The method of claim 18 ,
wherein each scan chain generates a sequence of test responses on the basis of the processing of the test data; and wherein the compression circuit compresses the sequences of test responses generated by the scan chains to form a sequence of compressed test responses.

20 . The method of claim 18 , further comprising:
masking the compressed test response if it is to be masked in accordance with the masking data.

Assignees

• Infineon Technologies Ag

Inventors

• Tille Daniel
• Pfannkuchen Ulrike
• Janke Marcus

Classifications

• G01R31/318566 Primary

  Comparators; Diagnosing the device under test · CPC title

• G06F11/267

  Reconfiguring circuits for testing, e.g. LSSD, partitioning · CPC title

• G01R31/318547

  Data generators or compressors · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/3172

  Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing · CPC title