Variation Calibration For Envelope Tracking On Chip

Patent metadata

Field	Value
Publication number	US-2016373142-A1
Application number	US-201615250920-A
Country	US
Kind code	A1
Filing date	Aug 30, 2016
Priority date	Sep 1, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

Techniques and examples pertaining to variation calibration for envelope tracking on chip are described. Envelope tracking (ET) statistics among multiple wireless-capable mobile devices (e.g., smartphones) may be collected in laboratory. Optimal ET parameters may be determined based on ET statistics. An ET setting file may be generated for ET factory calibration. In production lines, the ET setting file may be loaded into each mobile device for ET factory calibration.

First claim

What is claimed is:

1 . A method of calibrating a plurality of parameters of a semiconductor chip implementable in a wireless communication device, the method comprising:
performing a first calibration to calibrate a first set of parameters of the plurality of parameters; loading a universal setting file comprising a plurality of setting values for a second set of parameters of the plurality of parameters; and performing a second calibration to calibrate the second set of parameters, wherein the plurality of setting values are predetermined by performing a comprehensive calibration matrix across a plurality of sample chips, and wherein the plurality of setting values serve as initial calibration values for the second set of parameters.

2 . The method of claim 1 , wherein:
each of the plurality of sample chips comprises a transmitter (TX) having an envelope tracking (ET) capability, the second set of parameters comprises a plurality of ET parameters pertinent to the ET capability, the performing of the comprehensive calibration matrix across the plurality of sample chips comprises applying modulated radio-frequency (RF) signals to a respective TX of each of the plurality of sample chips, and the performing of the second calibration comprises applying non-modulated RF signals to a respective TX of the semiconductor chip.

3 . The method of claim 2 , wherein the plurality of ET parameters comprise one or more of an ET gain mapping, a digital pre-distortion (DPD) function, a bias voltage of a power amplifier (PA) of the TX, and a bias current of the PA.

4 . The method of claim 2 , wherein the TX is configured to transmit a signal at one of a plurality of signal frequencies, with each of the plurality of signal frequencies denoted by a respectively different combination of a band setting, a sub-band setting, a channel bandwidth (CBW) setting and a bandwidth configuration setting, and wherein the plurality of setting values of the universal setting file comprise a respective set of initial calibration values for each of the plurality of signal frequencies.

5 . The method of claim 4 , wherein the TX is further configured to transmit the signal at one of a plurality of RF power levels, and wherein the respective set of initial calibration values comprises a plurality of subsets of initial calibration values, with each of the plurality of subsets corresponding to a respective one of the plurality of RF power levels.

6 . A method, comprising:
performing a comprehensive calibration matrix across a plurality of sample chips to determine a plurality of setting values, the performing comprising:
collecting envelope tracking (ET) statistics among the plurality of sample chips;
determining a plurality of ET parameters based on the ET statistics; and
generating a universal setting file for the plurality of sample chips based on the plurality of ET parameters.

7 . The method of claim 6 , wherein the universal setting file is loaded into device under test as initial calibration values for a factory calibration.

8 . The method of claim 7 , wherein:
the performing of the comprehensive calibration matrix across the plurality of sample chips comprises applying modulated radio-frequency (RF) signals to a respective TX of each of the plurality of sample chips, and the performing of the factory calibration comprises applying non-modulated RF signals to a respective TX of the device under test.

9 . The method of claim 8 , wherein:
the plurality of ET parameters comprise one or more of an ET gain mapping, a digital pre-distortion (DPD) function, a bias voltage of a power amplifier (PA) of the TX, and a bias current of the PA, the TX is configured to transmit a signal at one of a plurality of signal frequencies, with each of the plurality of signal frequencies denoted by a respectively different combination of a band setting, a sub-band setting, a channel bandwidth (CBW) setting and a bandwidth configuration setting, the plurality of setting values of the universal setting file comprise a respective set of initial calibration values for each of the plurality of signal frequencies, the TX is further configured to transmit the signal at one of a plurality of RF power levels, and the respective set of initial calibration values comprises a plurality of subsets of initial calibration values, with each of the plurality of subsets corresponding to a respective one of the plurality of RF power levels.

10 . A variation calibration apparatus that calibrates a plurality of envelope tracking (ET) parameters for a plurality of semiconductor chips having a same circuit design, the circuit design comprising a transmitter (TX), the apparatus comprising:
a receptacle capable of receiving and operating each of the plurality of semiconductor chips one at a time; a variable power supply capable of setting a supply voltage through the receptacle for a respective semiconductor chip of the plurality of semiconductor chips received in the receptacle; a test instrument capable of measuring electrical characteristics of the respective semiconductor chip; a memory storing a plurality of ET setting combinations based on the plurality of ET parameters, with each of the ET parameters having respective one or more ET parameter settings, and the memory also storing a respective result of an ET measurement for each of the plurality of semiconductor chips; and a processor communicatively coupled to the receptacle, the variable power supply, the test instrument, and the memory, the processor capable of performing operations comprising:
performing the ET measurement for each of the plurality of semiconductor chips under one or more of a plurality of measurement conditions and under each of the plurality of ET setting combinations; and
analyzing the respective result of the ET measurement to determine a respective universal ET setting combination for each of one or more measurement conditions, and generating an ET setting file comprising one or more respective universal ET setting combinations for the one or more measurement conditions.

11 . The apparatus of claim 10 , wherein the electrical characteristics comprise one or more of an out-band emission, an in-band linearity, an error vector magnitude (EVM), an adjacent channel leakage ratio (ACLR), a receive-band noise (RXBN), a power efficiency, a current consumption, and a junction temperature.

12 . The apparatus of claim 10 , wherein the plurality of ET parameters comprise one or more of an ET gain mapping, a digital pre-distortion (DPD) function, a bias voltage of a power amplifier (PA) of the TX, and a bias current of the PA, and wherein each of the plurality of ET setting combinations comprises a respectively different combination of the plurality of ET parameters each set at one of the respective one or more ET parameter settings.

13 . The apparatus of claim 10 , wherein a respective one of the plurality of measurement conditions comprises a respectively different combination of a setting of the band, a setting of the sub-band, a setting of the CBW, and a setting of the bandwidth configuration, and wherein the ET measurement under the respective one of the plurality of measurement conditions is performed with a modulated radio-frequency (RF) signal modulated according to the setting of the band, the setting of the sub-band, the setting of the CBW, and the setting of the bandwidth configuration.

14 . The apparatus of claim 13 , wherein the respectively different combination further comprises a setting of a RF power, and wherein the modulated RF signal is further modulated to have a RF power

Assignees

• Mediatek Inc

Inventors

• Chen Yen-Liang
• Peng Chia-Sheng
• Sung Da-Wei

Classifications

• H03F3/195

  in integrated circuits · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H04B17/11

  for calibration · CPC title

• G01R31/2851

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title

• G01R19/04

  Measuring peak values {or amplitude or envelope} of AC or of pulses · CPC title