FinFETs with Strained Well Regions

Patent metadata

Field	Value
Publication number	US-2016372579-A1
Application number	US-201615253958-A
Country	US
Kind code	A1
Filing date	Sep 1, 2016
Priority date	Feb 27, 2013
Publication date	Dec 22, 2016
Grant date	—

Abstract

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

First claim

What is claimed is:

1 . A method comprising:
depositing a first semiconductor layer on a top surface and sidewalls of a semiconductor fin, wherein the semiconductor fin protrudes over top surfaces of isolation regions proximal the semiconductor fin, and the first semiconductor layer is undoped with n-type impurities during the depositing; depositing a second semiconductor layer over the first semiconductor layer, with the second semiconductor layer doped with an n-type impurity; depositing a third semiconductor layer over the second semiconductor layer; forming a gate dielectric over the third semiconductor layer; forming a gate electrode over the gate dielectric; and forming a source region and a drain region on opposite sides of the semiconductor fin.

2 . The method of claim 1 further comprising doping an n-type impurity into the third semiconductor layer during the depositing the third semiconductor layer, wherein the third semiconductor layer is doped to a lower n-type impurity concentration than the second semiconductor layer.

3 . The method of claim 1 , wherein during the depositing the third semiconductor layer, no n-type impurity is doped.

4 . The method of claim 1 , wherein the first semiconductor layer is further undoped with p-type impurities during the depositing the first semiconductor layer.

5 . The method of claim 1 further comprising doping the source region and the drain region with an n-type impurity.

6 . The method of claim 1 further comprising:
recessing a portion of a semiconductor substrate between isolation regions to form a recess;
performing a first epitaxy to grow a first semiconductor region in the recess, wherein the first semiconductor region is relaxed;
performing a second epitaxy to grow a second semiconductor region in the recess, wherein the second semiconductor region is over and contacting the first semiconductor region;
performing a planarization to level top surfaces of the second semiconductor region and the isolation regions; and
recessing the isolation regions, wherein a top portion of the second semiconductor region over the isolation regions forms the semiconductor fin.

7 . The method of claim 6 , wherein the first semiconductor region and the first, the second, and the third semiconductor layers comprise silicon germanium having first germanium atomic percentages, and wherein the second semiconductor region comprises silicon, with a second germanium atomic percentage in the second semiconductor region being lower than the first germanium atomic percentages.

8 . The method of claim 1 further comprising growing a silicon cap over the third semiconductor layer, wherein the silicon cap is not doped with n-type and p-type impurities when the silicon cap is grown.

9 . A method comprising:
performing a first epitaxy to grow a first silicon germanium layer on a top surface and sidewalls of a semiconductor fin, wherein during the first epitaxy, no n-type impurity and p-type impurity are doped into the first silicon germanium layer; performing a second epitaxy to grow a second silicon germanium layer over the first silicon germanium layer, with the second silicon germanium layer doped with an n-type impurity to a first n-type impurity concentration; performing a third epitaxy to grow a third silicon germanium layer over the second silicon germanium layer, with the second silicon germanium layer un-doped with n-type impurity during the third epitaxy; and forming a source region and a drain region on opposite sides of the semiconductor fin, wherein the source region and the drain region are n-type regions.

10 . The method of claim 9 further comprising depositing a silicon cap over the third silicon germanium layer, wherein the silicon cap is substantially free from germanium.

11 . The method of claim 10 , wherein no n-type impurity is added into the silicon cap during depositing the silicon cap.

12 . The method of claim 11 , wherein no p-type impurity is added into the silicon cap during depositing the silicon cap.

13 . The method of claim 10 further comprising, when the silicon cap is deposited, doping an n-type impurity into the silicon cap to a second n-type impurity concentration lower than the first n-type impurity concentration.

14 . The method of claim 9 further comprising:
forming a gate dielectric over the third silicon germanium layer; and
forming a gate electrode over the gate dielectric.

15 . The method of claim 9 further comprising:
recessing a portion of a semiconductor substrate between two isolation regions to form a recess;
performing a first epitaxy to grow a relaxed silicon germanium region in the recess;
performing a second epitaxy to grow an additional silicon germanium region in the recess, wherein the additional silicon germanium region is over and contacting the relaxed silicon germanium region, and the additional silicon germanium region has a germanium atomic percentage lower than germanium atomic percentages of the relaxed silicon germanium region and the first silicon germanium layer;
performing a planarization to level top surfaces of the additional silicon germanium region and the isolation regions; and
recessing the isolation regions, wherein a top portion of the additional silicon germanium region over the isolation regions forms the semiconductor fin.

16 . A method comprising:
performing an epitaxy to form a composite semiconductor region, wherein the composite semiconductor region comprises silicon germanium, and the composite semiconductor region comprises:
a first region having a first conduction band;
a second region over the first region, the second region having a second conduction band lower that the first conduction band; and
a third region over the second region, the third region having a third conduction band higher than the second conduction band;
forming a gate dielectric over the composite semiconductor region; forming a gate electrode over the gate dielectric; and forming a source region and a drain region, wherein the source region and the drain region are interconnected by the composite semiconductor region.

17 . The method of claim 16 , wherein each of the first region, the second region, and the third region comprises silicon germanium, and the second region has a germanium atomic percentage lower than germanium atomic percentages of the first region and the third region.

18 . The method of claim 16 , wherein the source region and the drain region are n-type regions, and when a first portion of the third region is grown, an n-type impurity is doped.

19 . The method of claim 18 , wherein when a second portion of the third region over the first portion is grown, no n-type impurity is doped.

20 . The method of claim 16 further comprising depositing a semiconductor cap region over the composite semiconductor region, wherein the source region and the drain region are n-type regions, and when the semiconductor cap region is deposited, no n-type impurity is doped.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Yi-Jing
• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/602

  Heterojunction gate electrodes for FETs · CPC title