Routing of nets of an integrated circuit

Patent metadata

Field	Value
Publication number	US-2016371401-A1
Application number	US-201514741504-A
Country	US
Kind code	A1
Filing date	Jun 17, 2015
Priority date	Jun 17, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

A routing specification is received for nets of an integrated circuit connecting source cells and sink cells in the integrated circuit. A target performance parameter is received for each of the nets, the target performance parameters specifying a propagation property of electrical signals in the nets. Layouts of the nets are generated according to the routing specification. An actual performance parameter for each of the nets in the layouts is generated, in which the actual performance parameters specify a calculated actual propagation property of electrical signals in the nets. A deviation parameter is generated for each of the performance parameters. Each of the deviation parameters is indicative of a degree of deviation of the respective actual performance parameter from its target performance parameter.

First claim

1 .- 10 . (canceled).

11 . A computer system for generating layouts of nets connecting source cells and sink cells in an integrated circuit, the computer system comprising:
a memory; and a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
receiving a routing specification for the nets of the integrated circuit and a target performance parameter for each of the nets, the target performance parameters specifying a propagation property of electrical signals in the nets;
generating layouts of the nets according to the routing specification;
generating an actual performance parameter for each of the nets in the layouts, the actual performance parameters specifying a calculated actual propagation property of electrical signals in the nets;
generating deviation parameters, each of the deviation parameters being indicative of a degree of deviation of the respective actual performance parameter from its target performance parameter; and
repetitively executing the following:
generating new layouts of the nets according to the routing specification, an order of the generation being determined by a ranking of each net, the ranking being performed according to a respective deviation parameter of each net;
generating an updated performance parameter for each of the new layouts; and
updating the deviation parameter for each of the new layouts with the respective updated performance parameter,

the repetitive execution being performed until a first condition or a second condition is fulfilled, the first condition comprising that at least one of the deviation parameters is less than a first threshold value, and the second condition comprising that for a present iteration a performance parameter for a new layout net has an improvement over a respective performance parameter of a previous iteration with the improvement being less than a second threshold value.

12 . The computer system of claim 11 , wherein the deviation parameter of said new layout net is bigger than deviation parameters of other nets for the present iteration.

13 . The computer system of claim 12 , wherein the method further comprises:
generating an indicator value for a set of the deviation parameters, the indicator value being a measure of a difference between a sum of the deviation parameters of the set of deviation parameters generated in the previous iteration and a sum of the deviation parameters of the set of deviation parameters generated in the present iteration, the second condition further comprising that the indicator value is less than a third threshold value.

14 . The computer system of claim 11 , wherein the ranking is described by a monotonically decreasing function of the deviation parameter, the generation of the new layouts of the nets according to the routing specification being performed first for the nets having a highest ranking.

15 . The computer system of claim 14 , wherein the method further comprises:
generating a monotonically increasing function of the deviation parameter, the monotonically increasing function specifying a maximum allowable rectilinear Steiner ratio for a correspondingly ranked net used for the generating of the new layouts of the nets according to the routing specification.

6 . A computer program product for generating layouts of nets connecting source cells and sink cells in an integrated circuit, the computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
receiving a routing specification for the nets of the integrated circuit and a target performance parameter for each of the nets, the target performance parameters specifying a propagation property of electrical signals in the nets;
generating layouts of the nets according to the routing specification;
generating an actual performance parameter for each of the nets in the layouts, the actual performance parameters specifying a calculated actual propagation property of electrical signals in the nets;
generating deviation parameters, each of the deviation parameters being indicative of a degree of deviation of the respective actual performance parameter from its target performance parameter; and
repetitively executing the following:
generating new layouts of the nets according to the routing specification, an order of the generation being determined by a ranking of each net, the ranking being performed according to a respective deviation parameter of each net;
generating an updated performance parameter for each of the new layouts; and
updating the deviation parameter for each of the new layouts with the respective updated performance parameter,

the repetitive execution being performed until a first condition or a second condition is fulfilled, the first condition comprising that at least one of the deviation parameters is less than a first threshold value, and the second condition comprising that for a present iteration a performance parameter for a new layout net has an improvement over a respective performance parameter of a previous iteration with the improvement being less than a second threshold value.

17 . The computer program product of claim 16 , wherein the deviation parameter of said new layout net is bigger than deviation parameters of other nets for the present iteration.

18 . The computer program product of claim 17 , wherein the method further comprises:
generating an indicator value for a set of the deviation parameters, the indicator value being a measure of a difference between a sum of the deviation parameters of the set of deviation parameters generated in the previous iteration and a sum of the deviation parameters of the set of deviation parameters generated in the present iteration, the second condition further comprising that the indicator value is less than a third threshold value.

19 . The computer program product of claim 16 , wherein the ranking is described by a monotonically decreasing function of the deviation parameter, the generation of the new layouts of the nets according to the routing specification being performed first for the nets having a highest ranking.

20 . The computer program product of claim 19 , wherein the method further comprises:
generating a monotonically increasing function of the deviation parameter, the monotonically increasing function specifying a maximum allowable rectilinear Steiner ratio for a correspondingly ranked net used for the generating of the new layouts of the nets according to the routing specification.

Assignees

• IBM

Inventors

• Beck Manuel
• Peyer Sven
• Schulte Christian
• Ziegler Wolfram

Classifications

• G06F17/505 Primary

  Physics · mapped topic

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title