Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016365299-A1
Application number	US-201615250492-A
Country	US
Kind code	A1
Filing date	Aug 29, 2016
Priority date	May 21, 2014
Publication date	Dec 15, 2016
Grant date	—

Abstract

A semiconductor device includes a semiconductor element, a substrate, a lead, and a sealing resin member. The semiconductor element has a first electrode and a second electrode located on opposite sides in the thickness direction. The substrate has an insulating base and a conductive plate. The base has first and second surfaces located on opposite sides in the thickness direction. The conductive plate is bonded to the first surface of the base and electrically connected to the second electrode of the semiconductor element. The lead has an island electrically connected to the first electrode. The sealing resin member covers at least the semiconductor element.

First claim

1 - 45 . (canceled)

46 . A semiconductor device comprising:
at least one semiconductor element including a first electrode and a second electrode that are opposite to each other in a thickness direction; a substrate including an insulating base and a conductive plate, the insulating base including an obverse surface and a reverse surface that are opposite to each other in the thickness direction, the conductive plate being bonded to the obverse surface of the base and electrically connected to the second electrode of the semiconductor element; a lead electrically connected to the first electrode; and a sealing resin member covering the semiconductor element.

47 . The semiconductor device according to claim 46 , wherein the lead includes at least one island.

48 . The semiconductor device according to claim 46 , wherein the lead is formed with a plurality of recesses.

49 . The semiconductor device according to claim 46 , wherein the conductive plate is made up of a plurality of members that are electrically insulated from each other.

50 . The semiconductor device according to claim 46 , further comprising a transistor, wherein the conductive plate is made up of at least a first member and a second member that are electrically insulated from each other, the first member being electrically connected to an electrode of the transistor, the second member being electrically connected to another electrode of the transistor.

51 . The semiconductor device according to claim 50 , wherein the first member and the second member of the conductive plate are different in size from each other.

52 . The semiconductor device according to claim 46 , further comprising a wire and a reinforced bonding portion, wherein the wire includes a bonding portion and a step portion, the bonding portion of the wire being bonded to one of the conductive plate and the lead, the step portion being connected to the bonding portion of the wire, and
wherein the reinforced bonding portion overlaps with at least a part of the bonding portion of the wire and exposes the step portion.

53 . The semiconductor device according to claim 46 , wherein the sealing resin member includes at least a first edge and a second edge that cross each other in plan view, and the first edge is formed with at least one first groove.

54 . The semiconductor device according to claim 53 , wherein the second edge of the sealing resin member is formed with a second groove.

55 . The semiconductor device according to claim 46 , wherein the base is made of ceramic.

56 . The semiconductor device according to claim 55 , wherein the base is made of alumina.

57 . The semiconductor device according to claim 46 , wherein the conductive plate is made of a metal.

58 . The semiconductor device according to claim 57 , wherein the conductive plate is made of Cu.

59 . The semiconductor device according to claim 46 , wherein the conductive plate is not smaller in thickness than the base.

60 . The semiconductor device according to claim 46 , further comprising a heat dissipation plate bonded to the reverse surface of the base.

61 . The semiconductor device according to claim 60 , wherein the heat dissipation plate has an exposed surface exposed from the sealing resin member.

62 . The semiconductor device according to claim 61 , wherein the exposed surface is flush with one surface of the sealing resin member.

63 . The semiconductor device according to claim 60 , wherein the heat dissipation plate is made of a metal.

64 . The semiconductor device according to claim 63 , wherein the heat dissipation plate is made of Cu.

65 . The semiconductor device according to claim 60 , wherein the heat dissipation plate is not smaller in thickness than the base.

66 . The semiconductor device according to claim 47 , wherein the at least one semiconductor element includes a plurality of semiconductor elements, and the island of the lead is electrically connected to the first electrodes of the plurality of semiconductor elements.

67 . The semiconductor device according to claim 46 , wherein the lead includes a conductive portion electrically connected to the conductive plate.

68 . The semiconductor device according to claim 47 , wherein the island is formed with a plurality of recesses.

69 . The semiconductor device according to claim 68 , wherein the island has a smooth part that overlaps with the semiconductor element.

70 . The semiconductor device according to claim 68 , wherein each of the recesses is circular in section.

71 . The semiconductor device according to claim 68 , wherein the plurality of recesses are arranged to surround the semiconductor element.

72 . The semiconductor device according to claim 46 , wherein the semiconductor element is a power semiconductor element through which an operating current flows.

73 . The semiconductor device according to claim 47 , further comprising a bonding material that bonds the first electrode and the island.

74 . The semiconductor device according to claim 46 , wherein the first electrode covers an entirety of one surface of the semiconductor element.

75 . The semiconductor device according to claim 73 , wherein the island is formed with a groove located outside the semiconductor element.

76 . The semiconductor device according to claim 75 , wherein the bonding material is disposed inside the groove.

77 . The semiconductor device according to claim 75 , wherein the groove surrounds the semiconductor element as a whole.

78 . The semiconductor device according to claim 75 , wherein the island is formed with a plurality of recesses located outside the groove.

79 . The semiconductor device according to claim 72 , further comprising a drive IC through which a control current flows for controlling the operating current.

80 . The semiconductor device according to claim 79 , further comprising a wire for connecting the drive IC and the conductive plate to each other.

81 . The semiconductor device according to claim 80 , wherein the conductive plate includes an extension that protrudes from the semiconductor element in plan view, and the wire has an end connected to the extension.

82 . The semiconductor device according to claim 81 , wherein the extension is provided with a bonding chip to which the wire is bonded.

83 . The semiconductor device according to claim 82 , wherein the bonding chip includes a lower layer and an upper layer laminated to the lower layer, the lower layer being closer to the conductive plate than is the upper layer.

84 . The semiconductor device according to claim 83 , wherein the lower layer is made of Cu.

85 . The semiconductor device according to claim 83 , wherein the upper layer is made of Ag.

86 . The semiconductor device according to claim 52 , wherein the reinforced bonding portion has a disk portion in contact with the bonding portion of the wire.

87 . The semiconductor device according to claim 86 , wherein the reinforced bonding portion has a column portion that is formed on the disk portion, is smaller in diameter

Assignees

• Rohm Co Ltd

Inventors

• Koga Akihiro

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title