Fin field effect transistor (finfet) device structure with interconnect structure

Patent metadata

Field	Value
Publication number	US-2016365271-A1
Application number	US-201514813775-A
Country	US
Kind code	A1
Filing date	Jul 30, 2015
Priority date	Jun 15, 2015
Publication date	Dec 15, 2016
Grant date	—

Abstract

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The semiconductor device structure further includes an adhesion layer formed in the dielectric layer and over the first metal layer and a second metal layer formed in the dielectric layer. The second metal layer is electrically connected to the first metal layer, and a portion of the adhesion layer is formed between the second metal layer and the dielectric layer. The adhesion layer includes a first portion lining with a top portion of the second metal layer, and the first portion has an extending portion along a vertical direction.

First claim

1 . A semiconductor device structure, comprising:
a first metal layer formed over a substrate; a dielectric layer formed over the first metal layer; an adhesion layer formed in the dielectric layer and over the first metal layer; and a second metal layer formed in the dielectric layer, wherein the second metal layer is electrically connected to the first metal layer, a portion of the adhesion layer is formed between the second metal layer and the dielectric layer, and wherein the adhesion layer comprises a first portion lining with a top portion of the second metal layer, and the first portion has an extending portion along a vertical direction.

2 . The semiconductor device structure as claimed in claim 1 , wherein the adhesion layer further comprises a second portion below the first portion, and the first portion is not connected to the second portion.

3 . The semiconductor device structure as claimed in claim 2 , wherein the second portion of the adhesion layer has a sloped top surface.

4 . The semiconductor device structure as claimed in claim 2 , wherein the extending portion has a tip located at a position that is lower than a highest position of the second portion.

5 . The semiconductor device structure as claimed in claim 1 , wherein the first portion of the adhesion layer has a first surface which is in direct contact with the dielectric layer and vertical to a top surface of the first metal layer, a lowest position of the first portion of the adhesion layer is at the first surface.

6 . The semiconductor device structure as claimed in claim 1 , wherein a bottom of the first portion of the adhesion layer has a smooth V-shaped shape.

7 . The semiconductor device structure as claimed in claim 1 , wherein the second metal layer comprises a via portion, an interface portion and a trench portion over the via portion, and the interface portion is formed between the via portion and the trench portion, and the interface portion has a pair of curved sidewalls.

8 . The semiconductor device structure as claimed in claim 1 , wherein a portion of the interface portion of the second metal layer has a tapered width that is gradually tapered from the trench portion towards to the via portion.

9 . The semiconductor device structure as claimed in claim 1 , wherein a portion of the interface portion of the second metal layer is in direct contact with the dielectric layer.

10 . A semiconductor device structure, comprising:
a first metal layer formed over a substrate; a dielectric layer formed over the first metal layer; an adhesion layer formed in the dielectric layer and over the first metal layer; and a second metal layer formed in the dielectric layer, wherein the adhesion layer is formed between the second metal layer and the dielectric layer, and the second metal layer comprises a via portion and a trench portion above the via portion, and wherein the adhesion layer comprises a first portion adjacent to the trench portion of the second metal layer, the first portion has an extending tip, and the extending tip is located at a position which is lower than a highest point of the via portion of the second metal layer.

11 . The semiconductor device structure as claimed in claim 10 , wherein the second metal layer further comprises an interface portion between the via portion and the trench portion, the via portion and the trench portion respectively have a constant width, the interface portion has a tapered width which is gradually tapped from the trench portion to the via portion.

12 . The semiconductor device structure as claimed in claim 10 , wherein the adhesion layer is a discontinuous layer.

13 . The semiconductor device structure as claimed in claim 10 , wherein the adhesion layer further comprises a second portion adjacent to the trench portion of the second metal layer.

14 . The semiconductor device structure as claimed in claim 13 , wherein the second portion of the adhesion layer has sloped top surface.

15 . The semiconductor device structure as claimed in claim 13 , wherein a bottom of the first portion of the adhesion layer has a smooth V-shaped shape.

16 . The semiconductor device structure as claimed in claim 15 , wherein the extending tip is located at a lowest position of the smooth V-shaped shape.

17 . The semiconductor device structure as claimed in claim 10 , wherein a bottom of the first portion of the adhesion layer has a first rounded sidewall connected to the extending tip and a second rounded sidewall connected to the extending tip, and the first rounded sidewall and the second rounded sidewall are symmetric in relation to the extending tip.

18 - 20 . (canceled)

21 . A semiconductor device structure, comprising:
a first metal layer formed over a substrate; a dielectric layer formed over the first metal layer; and a second metal layer formed in the dielectric layer, wherein the second metal layer is electrically connected to the first metal layer, the second metal layer comprises an upper portion, an middle portion and a lower portion, the middle portion is between the upper portion and the lower portion and the middle portion has a pair of curved sidewalls.

22 . The semiconductor device structure as claimed in claim 21 , further comprising:
an adhesion layer formed adjacent to the second metal layer, wherein the adhesion layer comprises a first portion in contact with a sidewall of the upper portion and a second portion in contact with a sidewall of the lower portion, and the first portion and the second portion are separated by the dielectric layer.

23 . The semiconductor device structure as claimed in claim 22 , wherein the first portion of the adhesion layer has an extended bottom surface in a horizontal direction.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Cheng
• Lin Chih-Han

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title