Read-out circuitry for an image sensor

Patent metadata

Field	Value
Publication number	US-2016360140-A1
Application number	US-201615242835-A
Country	US
Kind code	A1
Filing date	Aug 22, 2016
Priority date	Nov 29, 2013
Publication date	Dec 8, 2016
Grant date	—

Abstract

An array of image sensing elements is arranged in rows and columns. A readout circuit for each column includes a circuit configured to receive a column select signal. A memory stores data indicative of a voltage of an image sensing element which is being read. An analog to digital conversion circuit provides an output to the memory to control the storing of data. The output is dependent on the voltage of the image sensing element. Power control circuitry operates to disable, at least partially, the analog to digital conversion circuit when the column has not been selected.

First claim

What is claimed is:

1 . A circuit, comprising:
a column line; a column select circuit configured to select said column line; an analog to digital conversion circuit having an input coupled to receive an analog signal from said column line and configured to generate a digital output in response to said analog signal; and a power control circuit configured to selectively disable operation of the analog to digital conversion circuit when said column select circuit does not select said column.

2 . The circuit of claim 1 , further comprising an image sensing element connected to said column line, wherein said analog signal is a signal indicative of light detected by said image sensing element.

3 . The circuit of claim 1 , wherein the column select circuit outputs a column select signal and wherein said power control circuit selectively disables operation of the analog to digital conversion circuit in response to said column select signal.

4 . The circuit of claim 1 , wherein said analog to digital conversion circuit comprises a comparator circuit, and wherein said comparator circuit is selectively disabled by said power control circuit when said column select circuit does not select said column.

5 . The circuit of claim 1 , wherein said analog to digital conversion circuit comprises a sample and hold circuit, and wherein said sample and hold circuit is selectively disabled by said power control circuit when said column select circuit does not select said column.

6 . The circuit of claim 1 , further comprising a memory element configured to store said digital output.

7 . The circuit of claim 6 , wherein said memory element includes an input circuit configured to provide a low data input to said memory element when said column select circuit does not select said column.

8 . A circuit, comprising:
an array of row lines and column lines intersecting at pixels; a pixel select circuit configured to select a pattern of pixels in response to a row style signal; an analog to digital conversion circuit coupled to each column line; and a power control circuit configured to selectively disable operation of those analog to digital conversion circuits that are coupled to column lines associated with pixels that are not part of the pattern of pixels selected by the row style signal.

9 . The circuit of claim 8 , further comprising a column select circuit configured to select certain column lines, wherein said power control circuit is further configured to selectively disable operation of those analog to digital conversion circuits that are coupled to non-selected column lines.

10 . The circuit of claim 9 , wherein the column select circuit outputs a column select signal and wherein said power control circuit selectively disables operation of the analog to digital conversion circuits in response to said column select signal.

11 . The circuit of claim 8 , wherein said analog to digital conversion circuit comprises a comparator circuit, and wherein said comparator circuit is selectively disabled by said power control circuit.

12 . The circuit of claim 8 , wherein said analog to digital conversion circuit comprises a sample and hold circuit, and wherein said sample and hold circuit is selectively disabled by said power control circuit.

13 . The circuit of claim 8 , further comprising a memory element configured to store a digital output from said analog to digital conversion circuits.

14 . The circuit of claim 13 , wherein said memory element includes an input circuit configured to provide a low data input to said memory element when operation of said analog to digital conversion circuits is disabled.

Assignees

• Stmicroelectronics (Research & Development) Ltd

Inventors

• Raynor Jeffrey M

Classifications

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H04N25/44 Primary

  by partially reading an SSIS array · CPC title

• H04N25/445

  by skipping some contiguous pixels within the read portion of the array · CPC title

• H04N25/441

  by reading contiguous pixels from selected rows or columns of the array, e.g. interlaced scanning · CPC title

• H04N25/709

  Circuitry for control of the power supply · CPC title