Single-lane, twenty-five gigabit ethernet

Patent metadata

Field	Value
Publication number	US-2016359754-A1
Application number	US-201615237689-A
Country	US
Kind code	A1
Filing date	Aug 16, 2016
Priority date	May 21, 2014
Publication date	Dec 8, 2016
Grant date	—

Abstract

Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.

First claim

1 . A network port logic for high-speed data transmission, the network port logic comprising:
circuitry for receiving first serial binary data via a first communication lane at a first line transmission speed; means for converting, by a physical medium dependent sublayer/physical medium attachment sublayer (PMD/PMA) logic of the network port logic, the first serial binary data to first parallel data; means for decoding, by a physical coding sublayer (PCS) logic of the network port logic, the first parallel data to decoded parallel data using a line code also used by the PCS logic for serial binary data transmitted at a second line transmission speed, wherein the second line transmission speed is less than the first line transmission speed; and means for converting, by a media access control (MAC) logic of the network port logic, the decoded parallel data to first Ethernet frame data at a data rate determined by the first line transmission speed.

2 . The network port logic of claim 1 , wherein the means for decoding the first parallel data comprises means for decoding an encoded block, wherein the encoded block comprises an unscrambled sync symbol and a scrambled data section indicative of the decoded parallel data.

3 . The network port logic of claim 2 , wherein the encoded block comprises 66 bits, the sync symbol comprises two bits, and the scrambled data section comprises 64 bits indicative of 64 bits of decoded parallel data.

4 . The network port logic of claim 2 , wherein the encoded block further includes a scrambled control symbol.

5 . The network port logic of claim 1 , wherein the PMD/PMA logic comprises a serializer/deserializer (SERDES)

6 . The network port logic of claim 1 , further comprising:
circuitry for receiving second serial binary data via the first communication lane at the second line transmission speed; means for converting, by the PMD/PMA logic of the network port logic, the second serial binary data to second parallel data; means for decoding, by the PCS logic of the network port logic, the second parallel data to second decoded parallel data using the line code; and means for converting, by the MAC logic of the network port logic, the second decoded parallel data to second Ethernet frame data at a second data rate determined by the second line transmission speed.

7 . The network port logic of claim 6 , further comprising:
means for negotiating, with a link partner, whether to receive via the first transmission lane at the first line transmission speed or at the second line transmission speed; means for operating the PCS logic and the MAC logic at a core clock rate; and means for operating the PCS logic and the MAC logic at an effective clock rate lower than the core clock rate in response to negotiating to receive the second serial binary data at the second line transmission speed by generating a plurality of null operations to be executed by the PCS logic and the MAC logic.

8 . The network port logic of claim 1 , wherein the first line transmission speed comprises about 25 gigabits per second, the second line transmission speed comprises about 10 gigabits per second, and the data rate determined by the first line transmission speed comprises 25 gigabits per second.

9 . The network port logic of claim 8 , wherein the first line transmission speed comprises 25.78125 gigabits per second and the second line transmission speed comprises 10.3125 gigabits per second.

10 . The network port logic of claim 1 , further comprising:
means for negotiating, with a link partner, whether to receive via the first transmission lane at the first line transmission speed or at the second line transmission speed; means for executing a link training protocol in response to negotiating with the link partner to receive at the first line transmission speed; and means for executing the same link training protocol in response to negotiating with the link partner to receive at the second line transmission speed.

11 . The network port logic of claim 10 , wherein the means for executing the link training protocol comprises means for generating a signal pattern as a function of a predefined polynomial expression.

12 . The network port logic of claim 11 , wherein the first line transmission speed comprises about 25 gigabits per second, the second line transmission speed comprises about 10 gigabits per second, and the signal pattern comprises a PRBS 11 training pattern.

13 . The network port logic of claim 1 , further comprising:
circuitry for receiving, by the MAC logic of the network port logic, second Ethernet frame data at the data rate determined by the first line transmission speed; means for converting, by the MAC logic of the network port logic, the second Ethernet frame data to second parallel data; means for encoding, by the PCS logic of the network port logic, the second parallel data to encoded parallel data using the line code; means for converting, by the PMD/PMA logic of the network port logic, the encoded parallel data to second serial binary data; and circuitry for transmitting the second parallel binary data via the first communication lane at the first line transmission speed.

14 . The network port logic of claim 1 , further comprising:
circuitry for receiving second serial binary data via a second communication lane at the first line transmission speed; means for converting, by a second PMD/PMA logic of the network port logic, the second serial binary data to second parallel data; means for decoding, by a second physical coding sublayer (PCS) logic of the network port logic, the second parallel data to second decoded parallel data using the line code; means for converting, by a second media access control (MAC) logic of the network port logic, the second decoded parallel data to second Ethernet frame data at the data rate determined by the first line transmission speed; circuitry for receiving third serial binary data via a third communication lane at the first line transmission speed; means for converting, by a third PMD/PMA logic of the network port logic, the third serial binary data to third parallel data; means for decoding, by a third physical coding sublayer (PCS) logic of the network port logic, the third parallel data to third decoded parallel data using the line code; means for converting, by a third media access control (MAC) logic of the network port logic, the third decoded parallel data to third Ethernet frame data at the data rate determined by the first line transmission speed; circuitry for receiving fourth serial binary data via a fourth communication lane at the first line transmission speed; means for converting, by a fourth PMD/PMA logic of the network port logic, the fourth serial binary data to fourth parallel data; means for decoding, by a fourth physical coding sublayer (PCS) logic of the network port logic, the fourth parallel data to fourth decoded parallel data using the line code; and means for converting, by a fourth media access control (MAC) logic of the network port logic, the fourth decoded parallel data to fourth Ethernet frame data at the data rate determined by the first line transmission speed.

15 . The network port logic of claim 14 , further comprising:
circuitry for receiving fifth serial binary data via the first communication lane at the first line transmission speed, sixth serial binary data via the second communication lane at the first line transmission speed, seventh serial binary data via the third communication lane at the first line transmission speed, and eighth serial binary data via the fourth commun

Assignees

• Intel Corp

Inventors

• Gravel Alain
• Southworth Robert G
• Dama Jonathan A
• Ganga Ilango S
• Webb Matthew J

Classifications

• H04L1/0002

  by adapting the transmission rate · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L47/25 Primary

  with rate being modified by the source upon detecting a change of network conditions · CPC title

• H04L49/352

  Gigabit ethernet switching [GBPS] · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title