Semiconductor device including a resistive memory layer and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016359111-A1
Application number	US-201514883216-A
Country	US
Kind code	A1
Filing date	Oct 14, 2015
Priority date	Jun 8, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

2 . The method of claim 1 , wherein one or more of the interfacial conductive layer and the main conductive layer comprises one or more selected from a group consisting of W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, Mo, Ta, TiSi, TaSi, TiW, TiON, TiAlON, WON and TaON.

3 . The method of claim 2 , wherein the patterning of the main conductive layer comprises dry-etching the main conductive layer using an etching gas including Cl and/or F.

4 . The method of claim wherein the etch stop layer comprises carbon.

5 . The method of claim 4 , wherein the patterning of the portion of the etch stop layer comprises dry-etching the portion of the etch stop layer using an etching gas including N 2 /H 2 and/or N 2 /O 2 /Ar.

6 . The method of claim 1 , wherein the cleaning of the surface of the upper electrode structure and the surface of the resistive memory layer is performed using a buffered oxide etcher (BOE) chemical having a pH of about 6.5 to about 7.0 and/or a chemical including about 0.1% to about 5% by weight of an organic acid and having pH of about 3 to about 7.

7 . The method of claim 1 ,
wherein the patterning of the portion of the interfacial conductive layer comprises oxidizing the exposed portion of the interfacial conductive layer, wherein the cleaning of the surface of the upper electrode structure and the surface of the resistive memory layer removes the oxidized portion of the interfacial conductive layer, and wherein the cleaning of the surface of the upper electrode structure and the surface of the resistive memory layer removes byproducts generated in the patterning of the main conductive layer, the patterning of the portion of the etch stop layer and the patterning of the portion of the interfacial conductive layer.

8 . The method of claim 7 , wherein the oxidizing of the exposed portion of the interfacial conductive layer comprises wet-oxidizing the interfacial conductive layer using ozone water.

9 . The method of claim 7 , wherein the oxidizing of the exposed portion of the interfacial conductive layer comprises dry-oxidizing the interfacial conductive layer using plasma.

10 . The method of claim 7 , wherein the cleaning of the surface of the upper electrode structure and the surface of the resistive memory layer removes the oxidized portion of the interfacial conductive layer and the byproducts through a buffered oxide etcher (BOE) chemical having a pH of about 6.5 to about 7.0 and/or an NH 4 chemical having pH of about 10 to about 12.

11 . The method of claim 1 ,
further comprising forming a conductive layer as an adhesive layer between the etch stop layer and the main conductive layer, wherein the conductive layer is patterned simultaneously with the main conductive layer.

12 . A method of manufacturing a semiconductor device, the method comprising:
forming a resistive memory layer on a lower electrode; forming a barrier layer, which includes an interfacial conductive layer and an etch stop layer, on the resistive memory layer; forming a conductive layer on the barrier layer; forming an upper electrode by patterning the conductive layer until the etch stop layer is exposed; forming an etch stop layer pattern by patterning the etch stop layer using the upper electrode as an etch mask; forming a barrier layer pattern including an interfacial conductive layer pattern and an etch stop layer pattern by removing an exposed portion of the interfacial conductive layer; and forming a resistive memory layer pattern by etching the resistive memory layer using the upper electrode and the barrier layer pattern as etch masks.

13 . The method of claim 12 , wherein one or more of the interfacial conductive layer and the conductive layer comprises one or more selected from a group consisting of W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, Mo, Ta, TiSi, TaSi, TiW, TiON, TiAlON, WON and TaON.

14 . The method of claim 13 , wherein the patterning of the conductive layer comprises dry-etching the main conductive layer using an etching gas including Cl and/or F.

15 . The method of claim 12 , wherein the etch stop layer comprises carbon.

16 . The method of claim 15 , wherein the patterning of the etch stop layer comprises dry-etching the etch stop layer using an etching gas including N 2 /H 2 and/or N 2 /O 2 /Ar.

17 . The method of claim 12 , wherein the removing of the exposed portion of the interfacial conductive layer comprises:
dry-etching the exposed portion of the interfacial conductive layer; and cleaning the upper electrode, the barrier layer pattern and the resistive memory layer pattern.

18 . The method of claim 17 , wherein the cleaning of the upper electrode, the barrier layer pattern and the resistive memory layer pattern is performed using a buffered oxide etcher (BOE) chemical having a pH of about 6.5 to about 7.0 and/or a chemical including about 0.1% to about 5% by weight of an organic acid and having pH of about 3 to about 7.

19 . The method of claim 12 , wherein the removing of the exposed portion of the interfacial conductive layer comprises:
oxidizing the exposed portion of the interfacial conductive layer; and cleaning the oxidized portion of the interfacial conductive layer using a chemical.

20 . The method of claim 19 , wherein the oxidizing of the exposed portion of the interfacial conductive layer comprises wet-oxidizing the interfacial conductive layer using ozone water.

21 . The method of claim 19 , wherein the oxidizing of the exposed portion of the interfacial conductive layer comprises dry oxidizing the interfacial conductive layer using plasma.

22 . The method of claim 19 ,
wherein the chemical comprises a buffered oxide etcher (BOE) chemical having a pH of about 6.5 to about 7.0 and/or an NH 4 chemical having a pH of about 10 to about 12, and wherein the cleaning the oxidized portion of the interfacial conductive layer comprises removing byproducts.

23 . The method of claim 12 ,
wherein forming the barrier layer comprises forming a conductive adhesive layer on the etch stop layer, and wherein the conductive adhesive layer is patterned by the etching process for the forming of the upper electrode.

Assignees

• Sk Hynix Inc

Inventors

• Kim Gyu Hyun
• Kim Dae Won
• Lee Byoung Ki
• Cho Han Woo

Classifications

• H01L45/1608

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/1675 Primary

  Electricity · mapped topic

• H10N70/011 Primary

  Manufacture or treatment of multistable switching devices · CPC title

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title