Techniques for forming spin-transfer torque memory having a dot-contacted free magnetic layer

Patent metadata

Field	Value
Publication number	US-2016359101-A1
Application number	US-201415117605-A
Country	US
Kind code	A1
Filing date	Mar 28, 2014
Priority date	Mar 28, 2014
Publication date	Dec 8, 2016
Grant date	—

Abstract

Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

First claim

1 . An integrated circuit comprising:
a fixed magnetic layer; a first insulator layer formed over the fixed magnetic layer; a free magnetic layer formed over the first insulator layer; a second insulator layer formed over the free magnetic layer; an electrically conductive hardmask layer formed over the second insulator layer, wherein the hardmask layer has a width/diameter that is less than a width/diameter of the free magnetic layer; and a first dielectric spacer formed over the second insulator layer and covering sidewalls of the hardmask layer.

2 . The integrated circuit of claim 1 , wherein the fixed magnetic layer is electronically coupled with an underlying interconnect, and wherein the free magnetic layer is electronically coupled with an overlying interconnect.

3 . The integrated circuit of claim 1 , wherein each of the free magnetic layer and the hardmask layer has a width/diameter in the range of about 1-100 nm.

4 . The integrated circuit of claim 1 , wherein the hardmask layer is center-aligned with respect to the free magnetic layer.

5 . The integrated circuit of claim 1 , wherein the first dielectric spacer has a cylindrical geometry that is circular or elliptical in cross-sectional profile.

6 . The integrated circuit of claim 1 further comprising an encapsulation layer formed over a topography provided by the hardmask layer, the first dielectric spacer, the second insulator layer, the free magnetic layer, the first insulator layer, and the fixed magnetic layer.

7 . The integrated circuit of claim 1 further comprising a second dielectric spacer formed over the fixed magnetic layer and covering sidewalls of the free magnetic layer.

8 . The integrated circuit of claim 7 , wherein the second dielectric spacer has a cylindrical geometry that is circular or elliptical in cross-sectional profile.

9 . The integrated circuit of claim 7 further comprising an encapsulation layer formed over a topography provided by the hardmask layer, the first dielectric spacer, the second dielectric spacer, and the fixed magnetic layer.

10 . An embedded memory device comprising the integrated circuit of claim 1 .

11 . The embedded memory device of claim 10 , wherein the embedded memory device is a spin-torque transfer memory (STTM) device.

12 . A method of forming an integrated circuit, the method comprising:
forming a magnetic tunnel junction (MTJ) comprising a fixed magnetic layer, a first insulator layer over the fixed magnetic layer, and a free magnetic layer over the first insulator layer; forming a second insulator layer over the free magnetic layer; forming an electrically conductive hardmask layer over the second insulator layer; and forming a first dielectric spacer over the second insulator layer and covering sidewalls of the hardmask layer.

13 . The method of claim 12 further comprising:
patterning the fixed magnetic layer to reduce its width/diameter to about equal to a width/diameter of the free magnetic layer.

14 . The method of claim 12 , wherein forming the hardmask layer comprises:
depositing the hardmask layer over a topography provided by the second insulator layer; and patterning the hardmask layer to reduce its width/diameter to less than or about equal to a width/diameter of the second insulator layer.

15 . The method of claim 12 , wherein forming the first dielectric spacer comprises:
depositing the first dielectric spacer over a topography provided by the hardmask layer and the second insulator layer; and patterning the first dielectric spacer to reduce its dimensions to cover sidewalls of the hardmask layer.

16 . The method of claim 12 further comprising:
forming an encapsulation layer over a topography provided by the hardmask layer, the first dielectric spacer, the second insulator layer, the free magnetic layer, the first insulator layer, and the fixed magnetic layer.

17 . The method of claim 12 further comprising:
forming a second dielectric spacer over the fixed magnetic layer and covering sidewalls of the free magnetic layer.

18 . The method of claim 17 , wherein forming the second dielectric spacer comprises:
depositing the second dielectric spacer over a topography provided by the hardmask layer, the first dielectric spacer, the second insulator layer, and the free magnetic layer; and patterning the second dielectric spacer such that a lower portion of the second dielectric spacer resides either: below sidewalls of the free magnetic layer and above sidewalls of the first insulator layer; or below sidewalls of the first insulator layer and above sidewalls of the fixed magnetic layer.

19 . The method of claim 18 further comprising:
patterning the fixed magnetic layer to reduce its width/diameter to greater than a width/diameter of the free magnetic layer.

20 . The method of claim 18 further comprising:
forming an encapsulation layer over a topography provided by the hardmask layer, the first dielectric spacer, the second dielectric spacer, and the fixed magnetic layer.

21 . A spin-torque transfer memory (STTM) device comprising:
a fixed magnetic layer; a first magnesium oxide (MgO) layer formed over the fixed magnetic layer; a free magnetic layer formed over the first insulator layer; a second magnesium oxide (MgO) layer formed over the free magnetic layer; a metal-based hardmask layer formed over the second insulator layer, wherein the metal-based hardmask layer has a width/diameter that is less than a width/diameter of the free magnetic layer and is in the range of about 1-100 nm, and wherein the metal-based hardmask layer is electronically coupled with the free magnetic layer; and a first dielectric spacer formed over the second insulator layer and covering sidewalls of the metal-based hardmask layer, wherein the first dielectric spacer has a sidewall thickness in the range of about 1-20 nm.

22 . The STTM device of claim 21 further comprising a second dielectric spacer formed over the fixed magnetic layer and covering sidewalls of the free magnetic layer, wherein the second dielectric spacer has a sidewall thickness in the range of about 1-20 nm.

23 . The STTM device of claim 22 , wherein a lower portion of the second dielectric spacer resides either:
below sidewalls of the free magnetic layer and above sidewalls of the first insulator layer; or below sidewalls of the first insulator layer and above sidewalls of the fixed magnetic layer.

24 . The STTM device of claim 23 further comprising:
a lower electrode electronically coupled to the fixed magnetic layer; and
an upper electrode electronically coupled to the free magnetic layer.

25 . An embedded memory device comprising the STTM device of claim 21 .

Assignees

• Intel Corp

Inventors

• Kuo Charles C
• Oguz Kaan
• Doyle Brian S
• Doczy Mark L
• Kencke David L
• Suri Satyarth
• Chau Robert S

Classifications

• H01L43/12

  Electricity · mapped topic

• H01L43/08 Primary

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H10N50/80

  Constructional details · CPC title

• H10N50/01

  Manufacture or treatment · CPC title