Memory Devices and Methods of Manufacture Thereof

Patent metadata

Field	Value
Publication number	US-2016359052-A1
Application number	US-201615242193-A
Country	US
Kind code	A1
Filing date	Aug 19, 2016
Priority date	Dec 14, 2012
Publication date	Dec 8, 2016
Grant date	—

Abstract

Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.

First claim

What is claimed is:

1 . A method of manufacturing a memory device, the method comprising:
forming a tip recess in a workpiece; forming a first plate of a first capacitor, a first plate of a second capacitor, and a source region and a drain region of a transistor in the workpiece, at least a portion of the first plate of the first capacitor comprising the tip recess; forming an insulating material over the workpiece; forming a semiconductive material over the insulating material; and patterning the semiconductive material to form a gate of the transistor, a second plate of the first capacitor, and a second plate of the second capacitor, wherein the tip recess comprises a v-shape in a cross-sectional view, and the second plate of the first capacitor includes a tip portion that extends into the tip recess.

2 . The method of claim 1 , further comprising forming a plurality of shallow trench isolation (STI) regions in the workpiece.

3 . The method of claim 2 , wherein forming the tip recess comprises:
forming a masking material over the workpiece; patterning the masking material; and etching the workpiece using the masking material as an etch mask to form the tip recess.

4 . The method of claim 2 , wherein forming the plurality of STI regions and forming the tip recess occur simultaneously.

5 . The method of claim 4 , wherein forming the plurality of STI regions and forming the tip recess comprise:
forming a masking material over the workpiece; patterning the masking material; etching the workpiece using the masking material as an etch mask to form the tip recess and recesses for the plurality of STI regions; removing the masking material; forming an insulating material over the workpiece; removing the insulating material from over a top surface of the workpiece; and removing the insulating material from the tip recess.

6 . The method of claim 1 , wherein patterning the semiconductive material comprises forming a substantially continuous region of the semiconductive material that comprises the gate of the transistor, the second plate of the first capacitor, and the second plate of the second capacitor.

7 . A method of manufacturing a memory device, the method comprising:
forming a transistor having a gate disposed over a surface of a workpiece, and a source region and a drain region disposed in the workpiece proximate the gate, the source region and the drain region each extending from the surface of the workpiece into the workpiece; forming an erase gate including a tip portion that extends in a recess in the workpiece, the recess extending from the surface of the workpiece into the workpiece, wherein the erase gate contacts the gate of the transistor; and forming a coupling gate disposed over the workpiece, the coupling gate contacting the gate of the transistor.

8 . The method of claim 7 , wherein forming the transistor comprises integrally connecting the gate of the transistor to the erase gate.

9 . The method of claim 7 , further comprising disposing an insulating material between the tip portion of the erase gate and the workpiece.

10 . The method of claim 9 , wherein disposing the insulating material comprises depositing the insulating material to a thickness of about 70 Å or greater.

11 . The method of claim 7 , wherein forming the erase gate comprises extending the tip portion of the erase gate below a bottom surface of the gate of the transistor by about 50 Å to about 3,000 Å.

12 . The method of claim 7 , wherein forming the transistor comprises integrally connecting the gate of the transistor to the coupling gate.

13 . A method of manufacturing memory device, the method comprising:
forming a conductive electrode on a workpiece, the conductive electrode extending across a first region of the workpiece, a second region of the workpiece, and a third region of the workpiece; forming a first capacitor in the first region of the workpiece, the first capacitor comprising a first electrode in the workpiece and an erase gate electrode, the erase gate electrode being a first portion of the conductive electrode on the workpiece, the conductive electrode extending into a recess in the workpiece in the first region; forming a transistor in the second region of the workpiece, the transistor comprising a source/drain region in the workpiece and a gate, the gate being a second portion of the conductive electrode on the workpiece; and forming a second capacitor in the third region of the workpiece, the second capacitor comprising a second electrode in the workpiece and a coupling gate electrode, the coupling gate electrode being a third portion of the conductive electrode on the workpiece.

14 . The method of claim 13 , wherein forming the conductive electrode comprises forming a floating conductive electrode.

15 . The method of claim 13 further comprising disposing a dielectric layer between the conductive electrode and the workpiece.

16 . The method of claim 13 , wherein forming the first capacitor comprises forming the recess to have a v-shaped cross section.

17 . The method of claim 13 , wherein forming the first capacitor comprises forming the first electrode in a first doped region of the workpiece, and forming the second electrode in a second doped region of the workpiece.

18 . The method of claim 13 , wherein forming the conductive electrode comprises forming an L-shaped section of the conductive electrode in a plan view.

19 . The method of claim 13 , wherein forming the conductive electrode comprises forming a rectangular shaped section of the conductive electrode in a plan view.

20 . The method of claim 13 , wherein forming the first capacitor comprises extending a tip portion of the erase gate electrode below a bottom surface of the gate of the transistor by about 50 Å to about 3,000 Å.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kalnitsky Alexander
• Tuan Hsiao-Chin
• Tsui Felix Ying-Kit
• Lu Hau-Yan

Classifications

• G11C16/0441

  comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/6892

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D30/0411 Primary

  of FETs having floating gates · CPC title