Enhancement Mode III-N HEMTs

Patent metadata

Field	Value
Publication number	US-2016359030-A1
Application number	US-201615242266-A
Country	US
Kind code	A1
Filing date	Aug 19, 2016
Priority date	Apr 23, 2008
Publication date	Dec 8, 2016
Grant date	—

Abstract

A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

First claim

What is claimed is:

1 . A III-N semiconductor device, comprising:
a nitride channel layer including a first channel region beneath a conductive gate contact, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof; and a source contact and a drain contact, wherein the source contact and the gate contact are each over nitride channel layer and the drain contact is below on an opposite side of the nitride channel layer from the gate contact; wherein the first channel region is non-conductive in the absence of a switching voltage applied to the gate contact, but is conductive in the presence of a switching voltage greater than a threshold voltage applied to the gate contact.

2 . The device of claim 1 , wherein the device includes a GaN drift layer between the nitride channel layer and the drain contact.

3 . The device of claim 2 , wherein the GaN drift layer is a lightly doped (n−) layer.

4 . The device of claim 2 , wherein the device includes a current blocking layer between the nitride channel layer and the GaN drift layer.

5 . The device of claim 4 , wherein the current blocking layer is a doped GaN layer.

6 . The device of claim 4 , wherein the device includes channel access regions on opposite sides of the first channel region, and the current blocking layer is below the channel access regions but not below the first channel region.

7 . The device of claim 4 , wherein the device includes a substrate, and further comprises an additional nitride layer between the substrate and the GaN drift layer, wherein a via is formed through the substrate and the drain makes contact with the additional nitride layer through the via.

8 . The device of claim 7 , wherein the additional nitride layer comprises highly doped n+ GaN.

9 . The device of claim 1 , wherein the device includes channel access regions on opposite sides of the first channel region, wherein the device comprises an AlXN layer above the channel layer in the areas adjacent to the channel access regions but not in the area adjacent to the first channel region, wherein X is selected from the group consisting of gallium, indium or their combination.

10 . The device of claim 9 , wherein the device comprises an insulator layer between the gate contact and the nitride channel layer.

11 . The device of claim 1 , wherein the device is an enhancement mode device.

12 . A III-N semiconductor device, comprising:
a nitride channel layer including a first channel region beneath a conductive gate contact, and channel access regions on opposite sides of the first channel region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof; an AlXN layer above the channel layer, wherein X is selected from the group consisting of gallium, indium or their combination; and a source contact and a drain contact, wherein the source contact and the gate contact are each over the nitride channel layer and the drain contact is on an opposite side of the nitride channel layer from the gate contact; and a III-N drift layer between a substrate and the nitride channel layer; wherein a via is formed through the substrate and the drain contact is electrically connected to the III-N drift layer through the via in a first channel region beneath the gate contact.

13 . The device of claim 12 , wherein the concentration of Al and thickness of the AlXN layer is selected to induce a 2DEG charge in the channel access regions adjacent the AlXN layer without inducing any substantial 2DEG charge in the first channel region, so that a channel comprising the 2DEG charge is not conductive in the absence of a switching voltage applied to the gate, but is conductive when a switching voltage greater than a device threshold voltage is applied to the gate.

14 . The device of claim 13 , wherein the device is an enhancement mode device.

15 . The device of claim 12 , wherein the III-N drift layer is a lightly doped (n−) GaN layer.

16 . A III-N semiconductor device, comprising:
a nitride channel layer including a first channel region beneath a gate contact and channel access regions on opposite sides of the first channel region, the channel access regions connected to source contacts, wherein the composition of the nitride channel layer is selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof; a III-N layer above the nitride channel layer and surrounding the gate contact; a III-N drift layer below the nitride channel layer; and a drain contact connected to the III-N drift layer; wherein the first channel region is non-conductive in the absence of a switching voltage applied to the gate contact, but is conductive in the presence of a switching voltage greater than a threshold voltage applied to the gate contact.

17 . The device of claim 16 , wherein the III-N drift layer is a lightly doped (n−) GaN layer.

18 . The device of claim 17 , wherein the device includes a doped GaN current blocking layer between the nitride channel layer and the GaN drift layer.

19 . The device of claim 18 , wherein the GaN current blocking layer is below the channel access regions but not below the first channel region.

20 . The device of claim 16 , wherein the device is an enhancement mode III-N device.

Assignees

• Transphorm Inc

Inventors

• Mishra Umesh
• Coffie Robert
• Shen Likun
• Ben-Yaacov Ilan
• Parikh Primit

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/477 Primary

  Vertical HEMTs or vertical HHMTs · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title