Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016359028-A1
Application number	US-201615239201-A
Country	US
Kind code	A1
Filing date	Aug 17, 2016
Priority date	Dec 3, 2014
Publication date	Dec 8, 2016
Grant date	—

Abstract

In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a P-N junction including an anode P-type layer formed in the main surface of a semiconductor substrate and a back surface N + -type layer formed in the back surface of the semiconductor substrate, a back surface P + -type layer is formed in the back surface, and a surface P + -type layer is formed in the main surface right above the back surface P + -type layer to thereby promote the effect of hole injection from the back surface.

First claim

What is claimed is:

1 . A semiconductor device that comprises a diode, the diode comprising:
a semiconductor substrate that includes a first region and a second region which are adjacent to each other; a first P-type layer in a main surface of the semiconductor substrate in the first region; a second P-type layer in the main surface of the semiconductor substrate in the second region; a first N-type layer in the back surface on the opposite side of the main surface of the semiconductor substrate in the first region; a third P-type layer in the back surface of the semiconductor substrate in the second region; a second N-type layer in the semiconductor substrate and contacts each of the first N-type layer and the third P-type layer; a semiconductor layer between the second N-type layer and the first and second P-type layers; a first electrode electrically coupled with each of the first and second P-type layers; and a second electrode electrically coupled with the first N-type layer and the third P-type layer, wherein the second P-type layer is above the third P-type layer in a plan view.

2 . The semiconductor device according to claim 1 ,
wherein the impurities concentration of the third P-type layer is higher than that of the second N-type layer.

3 . The semiconductor device according to claim 1 ,
wherein the second P-type layer has an annular pattern in the plan view, and wherein a part of the first P-type layer in the main surface of the semiconductor substrate is inside of the annular pattern.

4 . The semiconductor device according to claim 1 ,
wherein the second P-type layer is 100 μm or less from an end of the third P-type layer toward the center of the third P-type layer in the direction along the main surface of the semiconductor substrate with the width of 50 μm or more in the direction along the main surface of the semiconductor substrate.

5 . The semiconductor device according to claim 1 ,
wherein the formation depth of the first P-type layer from the main surface of the semiconductor substrate is deeper than a formation depth of the second P-type layer from the main surface of the semiconductor substrate, and wherein a part of the first P-type layer contacts a lower surface of the second P-type layer in the second region.

6 . The semiconductor device according to claim 1 ,
wherein a formation depth of the first P-type layer from the main surface of the semiconductor substrate is shallower than the formation depth of the second P-type layer from the main surface of the semiconductor substrate.

7 . The semiconductor device according to claim 1 ,
wherein the area of the second P-type layer is smaller than the area of the third P-type layer in a plan view.

8 . The semiconductor device according to claim 1 ,
wherein an area of the second P-type layer is larger than the area of the third P-type layer in a plan view.

9 . The semiconductor device according to claim 1 ,
wherein a third N-type layer is between the semiconductor layer and the first P-type layer in the first region, and the impurities concentration of the third N-type layer is lower than that of the second N-type layer and higher than that of the semiconductor layer.

10 . The semiconductor device according to claim 1 ,
wherein the semiconductor layer is an N-type semiconductor layer or an intrinsic semiconductor layer.

11 . The semiconductor device according to claim 1 ,
wherein the width of the third P-type layer in the plan view is 200-400 μm.

12 . The semiconductor device according to claim 11 ,
wherein a width of the second P-type layer in a plan view is 200-400 μm.

13 . The semiconductor device according to claim 1 ,
wherein an area occupancy of the second P-type layer in the back surface of the semiconductor substrate is less than 30%.

14 . The semiconductor device according to claim 1 ,
wherein the impurities activation ratio of the second N-type layer is 60-70%.

15 . The semiconductor device according to claim 1 ,
wherein the semiconductor substrate includes a third region that is different from the first and second region, wherein, in the third region, a bipolar transistor is formed which includes a collector layer in the back surface of the semiconductor substrate, an emitter layer in the main surface of the semiconductor substrate, and a gate electrode over the main surface of the semiconductor substrate, wherein the emitter layer is electrically coupled with the first electrode, and wherein the collector layer is electrically coupled with the second electrode.

16 . The semiconductor device according to claim 1 ,
wherein the impurities concentration of the second N-type layer and the second P-type layer are higher than that of the semiconductor layer;
wherein the impurities concentration of the second P-type layer is higher than that of the first P-type layer, and
wherein the impurities concentration of the first N-type layer is higher than that of the second N-type layer.

Assignees

• Renesas Electronics Corp

Inventors

• Nakanishi Sho

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10D62/129

  Cathode regions of diodes · CPC title

• H10D62/128

  Anode regions of diodes · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title