CMOS Image Sensor

Patent metadata

Field	Value
Publication number	US-2016358960-A1
Application number	US-201615208169-A
Country	US
Kind code	A1
Filing date	Jul 12, 2016
Priority date	Dec 27, 2005
Publication date	Dec 8, 2016
Grant date	—

Abstract

A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor.

First claim

1 - 9 . (canceled)

10 . A method for forming an apparatus, wherein the method comprises:
forming a first gate electrode by:
forming a first gate insulation layer; and
forming a first polysilicon layer on the first gate insulation layer; and
forming a first silicide layer on only a portion of the first polysilicon layer.

11 . The method of claim 10 , wherein said forming a first silicide layer comprises a self-aligned silicide process.

12 . The method of claim 10 , wherein the first gate electrode is formed as a part of one of a select transistor, a transfer transistor, or a reset transistor.

13 . The method of claim 10 , wherein the first gate electrode is formed as a part of a select transistor.

14 . The method of claim 10 , further comprising:
forming a second gate electrode by:
forming a second gate insulation layer; and
forming a second polysilicon layer on the second gate insulation layer; and
forming a second silicide layer on only a portion of the second polysilicon layer.

15 . The method of claim 14 , wherein said forming a second silicide layer comprises a self-aligned silicide process.

16 . The apparatus of claim 14 , wherein:
the first gate electrode is formed as a part of one of a select transistor, a transfer transistor, or a reset transistor; and the second gate electrode is formed as a part of a different one of the select transistor, the transfer transistor, or the reset transistor.

17 . The method of claim 16 , wherein the first gate electrode is formed as a part of the select transistor.

18 . The method of claim 14 , further comprising:
forming a third gate electrode by:
forming a third gate insulation layer; and
forming a third polysilicon layer on the third gate insulation layer; and
forming a third silicide layer on only a portion of the third polysilicon layer.

19 . The method of claim 18 , wherein said forming a third silicide layer comprises a self-aligned silicide process.

20 . The method of claim 18 , wherein:
the first gate electrode is formed as a part of one of a select transistor, a transfer transistor, or a reset transistor; the second gate electrode is formed as a part of a different one of the select transistor, the transfer transistor, or the reset transistor; and the third gate electrode is formed as a part of the remaining one of the select transistor, the transfer transistor, or the reset transistor.

Assignees

• Intellectual Ventures Ii Llc

Inventors

• Lee Won-Ho

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H04N25/677

  for reducing the column or line fixed pattern noise · CPC title

• H04N25/67 Primary

  applied to fixed-pattern noise, e.g. non-uniformity of response · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H01L27/14614 Primary

  Electricity · mapped topic