Solid-state imaging device, manufacturing method thereof, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-2016358959-A1
Application number	US-201615239679-A
Country	US
Kind code	A1
Filing date	Aug 17, 2016
Priority date	Feb 25, 2011
Publication date	Dec 8, 2016
Grant date	—

Abstract

A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer.

First claim

What is claimed is:

1 . An imaging device, comprising:
a semiconductor substrate including a first side as a light-incident side and a second side opposite to the first side; a plurality of photoelectric conversion portions disposed in the semiconductor substrate; a pinning layer disposed at the first side of the semiconductor substrate; an insulating layer disposed on the pinning layer; a trench having a lattice shape in a plan view, wherein at least part of the trench is disposed between adjacent photoelectric conversion portions of the plurality of photoelectric conversion portions, the at least part of the trench including: a first portion including the pinning layer, and a second portion including the pinning layer and the insulating layer, wherein,
a width of the first portion is smaller than a width of the second portion in a cross-section view,
the insulating layer is disposed at an inner side of the pinning layer in the second portion in the cross-section view. and the insulating layer is not included in the first portion in the cross-section view.

2 . The imaging device according to claim 1 , wherein the insulating layer is in direct contact with an entirety of the inner side of the pinning layer in the second portion.

3 . The imaging device according to claim 1 , wherein the pinning layer is selected from the group consisting of hafnium oxide, zirconium dioxide, aluminum oxide, neodymium oxide, tantalum pentoxide, lanthanum oxide, praseodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, ytterbium oxide, lutetium oxide or yttrium oxide, and combinations thereof.

4 . The imaging device according to claim 1 , further comprising:
a pixel including at least one of the photoelectric conversion portions and a pixel transistor, wherein the pixel transistor and a wiring layer are disposed at the second side of the semiconductor substrate, wherein the first portion is disposed closer to the second side of the semiconductor substrate than the second portion.

5 . The imaging device according to claim 4 , wherein the pixel transistor includes at least a reset transistor, an amplification transistor, and a transfer transistor.

6 . The imaging device according to claim 1 , wherein a light-shielding portion is disposed corresponding to the trench.

7 . The imaging device according to claim 1 , wherein at least one of the photoelectric conversion portions includes a hole accumulation diode structure.

8 . The imaging device according to claim 1 , wherein a thickness of the insulating layer is 5 μm or less.

9 . The imaging device according to claim 1 , wherein the pinning layer comprises hafnium oxide that extends outside of the trench to a surface of the semiconductor substrate.

10 . An imaging device, comprising:
a plurality of photoelectric conversion portions disposed in a semiconductor substrate; a trench having a lattice shape in a plan view, wherein at least part of the trench is disposed between adjacent photoelectric conversion portions of the plurality of photoelectric conversion portions, the at least part of the trench including: a first portion including a pinning layer, and a second portion including the pinning layer and an insulating layer, wherein,
a width of the first portion is smaller than a width of the second portion in a cross-section view,
the insulating layer is disposed at an inner side of the pinning layer in the second portion in the cross-section view, and the insulating layer is not included in the first portion in the cross-section view.

11 . The imaging device according to claim 10 , wherein the semiconductor substrate comprises a first side as a light-incident side and a second side opposite to the first side, wherein the plurality of photoelectric conversion portions are disposed in the semiconductor substrate, wherein the pinning layer is disposed at the first side of the semiconductor substrate, and wherein the insulating layer is disposed on the pinning layer at the first side of the semiconductor substrate.

12 . The imaging device according to claim 11 , wherein the insulating layer is in direct contact with an entirety of the inner side of the pinning layer in the second portion.

13 . The imaging device according to claim 10 , wherein the pinning layer is selected from the group consisting of hafnium oxide, zirconium dioxide, aluminum oxide, neodymium oxide, tantalum pentoxide, lanthanum oxide, praseodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, ytterbium oxide, lutetium oxide or yttrium oxide, and combinations thereof.

14 . The imaging device according to claim 10 , further comprising:
a pixel including at least one of the photoelectric conversion portions and a pixel transistor, wherein the pixel transistor and a wiring layer are disposed at the second side of the semiconductor substrate, wherein the first portion is disposed closer to the second side of the semiconductor substrate than the second portion.

15 . The imaging device according to claim 14 , wherein the pixel transistor includes at least a reset transistor, an amplification transistor, and a transfer transistor.

16 . The imaging device according to claim 10 , wherein a light-shielding portion is disposed corresponding to the trench.

17 . The imaging device according to claim 10 , wherein at least one of the photoelectric conversion portions includes a hole accumulation diode structure.

18 . The imaging device according to claim 10 , wherein a thickness of the insulating layer is 5 μm or less.

19 . The imaging device according to claim 10 , wherein the pinning layer comprises hafnium oxide that extends outside of the trench to a surface of the semiconductor substrate.

20 . An imaging device, comprising:
a semiconductor substrate including a first side as a light-incident side and a second side opposite to the first side; a plurality of photoelectric conversion portions disposed in the semiconductor substrate; a pinning layer disposed at the first side of the semiconductor substrate; an insulating layer disposed on the pinning layer; a trench having a lattice shape in a plan view, wherein at least part of the trench is disposed between adjacent photoelectric conversion portions of the plurality of photoelectric conversion portions, the at least part of the trench including: a first portion including the pinning layer, and a second portion including the pinning layer and the insulating layer, wherein,
a width of the first portion is smaller than a width of the second portion in a cross-section view,
the insulating layer is not included in the first portion in the cross-section view.

21 . The imaging device according to claim 20 , wherein the insulating layer is disposed at an inner side of the pinning layer in the second portion in the cross-section view.

22 . The imaging device according to claim 21 , wherein the insulating layer is in direct contact with an entirety of the inner side of the pinning layer in the second portion.

23 . The imaging device according to claim 20 , wherein the pinning layer is selected from the group consisting of hafnium oxide, zirconium dioxide, aluminum oxide, neodymium oxide, tantalum pentoxide, lanthanum oxide, praseodymium oxide,

Assignees

• Sony Corp

Inventors

• Enomoto Takayuki

Classifications

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H01L27/14623

  Electricity · mapped topic

• H01L27/14685

  Electricity · mapped topic

• H01L27/14627

  Electricity · mapped topic