Oxide Semiconductor TFT Array Substrate and Method for Manufacturing the Same

Patent metadata

Field	Value
Publication number	US-2016358944-A1
Application number	US-201615170433-A
Country	US
Kind code	A1
Filing date	Jun 1, 2016
Priority date	Jun 3, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A method for manufacturing an oxide semiconductor TFT array substrate is provided, which including: successively depositing an oxide semiconductor active layer and a transparent conductive layer on a base substrate without breaking vacuum; and forming patterns of an active layer and a transparent conductive layer. An oxide semiconductor TFT array substrate is further provided.

First claim

What is claimed is:

1 . A method for manufacturing an oxide semiconductor array substrate, comprising:
successively depositing an oxide semiconductor active layer and a transparent conductive layer on a base substrate without breaking vacuum; and forming patterns of an active layer and a transparent conductive layer through one patterning process.

2 . The method according to claim 1 , before successively depositing the oxide semiconductor active layer and the transparent conductive layer on the base substrate without breaking vacuum, the method further comprising:
forming a gate metal layer; and forming a pattern of a gate electrode by one patterning process.

3 . The method according to claim 1 , wherein after successively depositing the oxide semiconductor active layer and the transparent conductive layer on the base substrate without breaking vacuum and before forming the patterns of the active layer and the transparent conductive layer, the method further comprises:
forming a source/drain metal layer on the transparent conductive layer.

4 . The method according to claim 3 , wherein an operation of forming patterns of the active layer and the transparent conductive layer through one patterning process comprises:
forming patterns of source/drain electrodes, the transparent conductive layer, and the active layer through one patterning process.

5 . The method according to claim 4 , wherein an operation of forming patterns of source/drain electrodes, the transparent conductive layer, and the active layer through one patterning process comprises:
forming a photoresist layer on the source/drain metal layer; exposing the photoresist layer through a half-tone mask and developing; removing portions of the source/drain metal layer other than a portion of the source/drain metal layer configured to form the source/drain electrodes and a portion of the source/drain metal layer within in an effective display area of a pixel unit; performing a first ashing process on retained photoresist layer after developing, so as to expose a region of the source/drain metal layer in a channel region to be formed; etching the exposed portion of the source/drain metal layer in the channel region to be formed so as to form the channel region; partially etching a portion of the transparent conductive layer within the channel region in a direction along a thickness of the transparent conductive layer; performing a second ashing process on the retained photoresist layer so as to expose a portion of the transparent conductive layer other than a portion of the transparent conductive layer for a drain electrode connected with a data line; removing the portion of the transparent conductive layer other than the portion of the transparent conductive layer for the drain electrode connected with the data line; and removing a portion of the transparent conductive layer retained in the channel region.

6 . The method according to claim 2 , wherein after successively depositing the oxide semiconductor active layer and the transparent conductive layer on the base substrate without breaking vacuum and before forming the patterns of the active layer and the transparent conductive layer, the method further comprises:
forming a source/drain metal layer on the transparent conductive layer.

7 . The method according to claim 6 , wherein forming patterns of the active layer and the transparent conductive layer through one patterning process comprises:
forming patterns of source/drain electrodes, the transparent conductive layer and the active layer through one patterning process.

8 . The method according to claim 7 , wherein an operation of forming patterns of source/drain electrodes, the transparent conductive layer and the active layer through one patterning process comprises:
forming a photoresist layer on the source/drain metal layer; exposing the photoresist layer through a half-tone mask and developing; removing portions of the source/drain metal layer other than a portion of the source/drain metal layer configured to form source/drain electrodes and a portion of the source/drain metal layer within in an effective display area of a pixel unit; performing a first ashing process on retained photoresist layer after developing, so as to expose a region of the source/drain metal layer in a channel region to be formed; etching the exposed portion of the source/drain metal layer in the channel region to be formed so as to form the channel region; partially etching a portion of the transparent conductive layer within the channel region in a direction along a thickness of the transparent conductive layer; performing a second ashing process on the retained photoresist layer so as to expose a portion of the transparent conductive layer other than a portion of the transparent conductive layer for a drain electrode connected with a data line; removing the portion of the transparent conductive layer other than the portion of the transparent conductive layer for the drain electrode connected with the data line; and removing a portion of the transparent conductive layer retained in the channel region.

9 . The method according to claim 1 , wherein after forming patterns of an active layer and a transparent conductive layer through one patterning process, the method further comprises:
forming a gate metal layer, and forming a pattern of gate electrode through one patterning process.

10 . The method according to claim 9 , wherein after successively depositing the oxide semiconductor active layer and the transparent conductive layer on the base substrate without breaking vacuum and before forming the patterns of the active layer and the transparent conductive layer, the method further comprises:
forming a source/drain metal layer on the transparent conductive layer.

11 . The method according to claim 10 , wherein an operation of forming patterns of the active layer and the transparent conductive layer through one patterning process comprises:
forming patterns of source/drain electrodes, the transparent conductive layer and the active layer through one patterning process.

12 . The method according to claim 11 , wherein an operation of forming patterns of source/drain electrodes, the transparent conductive layer and the active layer through one patterning process comprises:
forming a photoresist layer on the source/drain metal layer; exposing the photoresist layer through a half-tone mask and developing; removing portions of the source/drain metal layer other than a portion of the source/drain metal layer configured to form source/drain electrodes and a portion of the source/drain metal layer within in an effective display area of a pixel unit; performing a first ashing process on retained photoresist layer after developing, so as to expose a region of the source/drain electrode in a channel region to be formed; etching the exposed portion of the source/drain metal layer in a channel region to be formed so as to form the channel region; partially etching a portion of the transparent conductive layer within the channel region in a direction along a thickness of the transparent conductive layer; performing a second ashing process on the retained photoresist layer so as to expose a portion of the transparent conductive layer other than a portion of the transparent conductive layer for the drain electrode connected with a data line; removing the portion of the transparent conductive layer other than the portion of the transparent conductive layer for the drain electrode connected with the data line; and removing a portion of the transparent conductive layer retained in th

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Yin Bingkun
• Han Junhao

Classifications

• H10P14/3426

  Oxides · CPC title

• H10D30/0312

  characterised by the gate electrodes · CPC title

• H10D30/6746

  Amorphous silicon · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title

• H10D30/6732

  Bottom-gate only TFTs · CPC title