Display device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2016358938-A1
Application number	US-201614991861-A
Country	US
Kind code	A1
Filing date	Jan 8, 2016
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A display device having a display area and a non-display area includes a substrate, a pixel at the display area, a signal line on the substrate and electrically connected to the pixel, and a static electricity prevention capacitor at the non-display area and including a lower pattern having a first region and a second region that have different electrical conductivities from each other, an insulating layer on the lower pattern, and an upper pattern including a portion of the signal line and overlapping the first region of the lower pattern in a plan view.

First claim

What is claimed is:

1 . A display device having a display area and a non-display area, the display device comprising:
a substrate; a pixel at the display area; a signal line on the substrate and electrically connected to the pixel; and a static electricity prevention capacitor at the non-display area and comprising:
a lower pattern having a first region and a second region that have different electrical conductivities from each other;
an insulating layer on the lower pattern; and
an upper pattern comprising a portion of the signal line and overlapping the first region of the lower pattern in a plan view.

2 . The display device of claim 1 , wherein the first region comprises an intrinsic semiconductor, and
wherein the second region comprises a semiconductor doped with impurities.

3 . The display device of claim 2 , wherein the signal line comprises at least one of:
a gate line extending in a first direction; or a data line extending in a second direction crossing the first direction.

4 . The display device of claim 3 , further comprising a floating pattern between the lower pattern and the upper pattern,
wherein the upper pattern comprises a portion of the data line.

5 . The display device of claim 3 , wherein the upper pattern comprises a portion of the gate line.

6 . The display device of claim 3 , wherein the pixel comprises:
a thin film transistor electrically connected to the gate line and the data line; and a light emitting device comprising:
a first electrode electrically connected to the thin film transistor;
a light emitting layer on the first electrode; and
a second electrode on the light emitting layer.

7 . The display device of claim 6 , wherein the thin film transistor comprises:
an active pattern on the substrate; a gate electrode on the active pattern; a source electrode electrically connected to the active pattern; and a drain electrode electrically connected to the active pattern, wherein the insulating layer comprises:
a first insulating layer between the active pattern and the gate electrode; and
a second insulating layer between the gate electrode and the source and drain electrodes.

8 . The display device of claim 7 , wherein the active pattern comprises:
a channel area comprising a same material as the first region and overlapping the gate electrode; a source area comprising a same material as the second region at one side of the channel area and connected to the source electrode; and a drain area comprising the same material as the second region at another side of the channel area opposite the source area and connected to the drain electrode.

9 . The display device of claim 8 , wherein the first region comprises an intrinsic semiconductor, and
wherein the second region comprises a semiconductor doped with impurities.

10 . The display device of claim 7 , wherein the upper pattern comprises:
a portion of the data line; and a bridge pattern on the first insulating layer that is electrically connected to the data line through a contact hole in the second insulating layer.

11 . The display device of claim 10 , wherein the bridge pattern comprises a same material as the gate line.

12 . The display device of claim 3 , wherein the signal line further comprises a power line in parallel to the data line on the substrate, and
wherein the display device further comprises:
a first thin film transistor electrically connected to the gate line and the data line; and
a second thin film transistor electrically connected to the first thin film transistor and the power line.

13 . The display device of claim 12 , further comprising a floating pattern between the lower pattern and the upper pattern,
wherein the upper pattern is a portion of the power line.

14 . A method of fabricating a display device having a display area and a non-display area, the method comprising:
preparing a substrate; forming a pixel at the display area of the substrate; and forming a static electricity prevention capacitor at the non-display area by:
forming a semiconductor pattern at the non-display area;
forming an insulating layer on the semiconductor pattern;
forming a signal line on the insulating layer to be electrically connected to the pixel; and
doping the semiconductor pattern with impurities while using a portion of the signal line as a mask to form a lower pattern having a first area and a second area.

15 . The method of claim 14 , wherein the signal line comprises at least one of:
a gate line extending in a first direction; or a data line extending in a second direction crossing the first direction.

16 . The method of claim 15 , wherein the portion of the signal line as a mask comprises the gate line.

17 . The method of claim 15 , wherein the signal line further comprises a floating pattern spaced from and insulated from the gate line, and
wherein the portion of the signal line as a mask comprises the floating pattern.

18 . The method of claim 15 , wherein the pixel comprises:
a thin film transistor electrically connected to the gate line and the data line; and a light emitting device comprising:
a first electrode electrically connected to the thin film transistor;
a light emitting layer on the first electrode; and
a second electrode on the light emitting layer.

19 . The method of claim 18 , wherein the thin film transistor includes:
an active pattern on the substrate; a gate electrode on the active pattern; a source electrode connected to the active pattern; and a drain electrode connected to the active pattern, wherein the insulating layer comprises:
a first insulating layer between the active pattern and the gate electrode; and
a second insulating layer between the gate electrode and the source and drain electrodes.

20 . The method of claim 19 , wherein the active pattern and the semiconductor pattern are formed during a same process.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Gi Chang
• Wang In Soo
• Lee Yong Soo

Classifications

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title