Array Substrate and Manufacturing Method Thereof and Display Panel

Patent metadata

Field	Value
Publication number	US-2016358937-A1
Application number	US-201514892459-A
Country	US
Kind code	A1
Filing date	Jun 18, 2015
Priority date	Dec 11, 2014
Publication date	Dec 8, 2016
Grant date	—

Abstract

An array substrate and manufacturing method thereof and a display panel are disclosed. The manufacturing method of an array substrate includes: forming patterns of a thin film transistor, a planarization layer and a passivation layer on a base substrate, the pattern of the thin film transistor including patterns of a gate electrode, a gate insulation layer, an active layer and source and drain electrodes; patterns of the planarization layer and the passivation layer are formed by one patterning process. With the manufacturing method of the array substrate, the number of patterning processes during manufacturing of the array substrate can be decreased. Furthermore, the size of via holes in the planarization layer and the passivation layer can be decreased, thereby increasing the aperture ratio of the display device and enhancing the display effect of images.

First claim

1 . A manufacturing method of an array substrate, comprising: forming patterns of a thin film transistor, a planarization layer and a passivation layer on a base substrate, a pattern of the thin film transistor including patterns of a gate electrode, a gate insulation layer, an active layer and source and drain electrodes,
wherein patterns of the planarization layer and the passivation layer are formed by one patterning process.

2 . The method claimed as claim 1 , further comprising,
after the pattern of the passivation layer is formed, forming a pattern of a pixel electrode layer that is connected to the drain electrode.

3 . The method claimed as claim 1 , further comprising: forming a pattern of a data line layer, the base substrate including a display region and a peripheral region that adjoins and surrounds the display region, the pattern of the data line layer including pattern of a data line provided in the display region and a lead pattern provided in the peripheral region, the lead pattern of the data line layer including a plurality of first leads arranged along a first direction and a plurality of second leads arranged along a second direction, and the first direction and the second direction being two different directions on a plane in parallel to the base substrate, wherein,
between the first leads or the second leads of the data line layer, connection is realized by lead connection lines of the pixel electrode layer provided in the peripheral region.

4 . The method claimed as claim 1 , further comprising forming a pattern of a common electrode layer on the pattern of the planarization layer, wherein, forming of the patterns of the planarization layer and the passivation layer includes:
forming a thin film of a planarization layer material on the pattern of the thin film transistor; forming a thin film of a passivation layer material on the pattern of the common electrode layer; with one patterning process, forming the thin film of the planarization layer material to the pattern of the planarization layer, and forming the thin film of the passivation layer material to the pattern of the passivation layer.

5 . The method claimed as claim 4 , wherein forming of the patterns of the planarization layer and the passivation layer includes: forming a plurality of via holes in the thin film of the planarization layer material and the thin film of the passivation layer material.

6 . The method claimed as claim 4 , wherein forming of the thin film of the planarization layer material to a pattern of the planarization layer and the thin film of the passivation layer material to a pattern of the passivation layer with one patterning process includes:
coating a layer of photoresist on the substrate with the thin film of the planarization layer material and the thin film of the passivation layer formed thereon; conducting exposure of the photoresist with a mask, and then performing development on the exposed photoresist, so that a photoresist fully-retained region and a photoresist fully-removed region are formed after development, wherein the photoresist fully-removed region corresponds to region of the drain electrode, and a rest region is the photoresist fully-retained region; removing the thin film of the planarization layer material and the thin film of the passivation layer material provided in the photoresist fully-removed region; and removing the remaining photoresist.

7 . The method claimed as claim 5 , further comprising:
forming a pattern of a common electrode layer with one patterning process on the thin film of the planarization layer material.

8 . The method claimed as claim 1 , wherein a material for the planarization layer is a resin material.

9 . The method claimed as claim 1 , wherein a material for the passivation layer is silicon nitride or a transparent, organic resin material.

10 . An array substrate, comprising: a thin film transistor, a planarization layer and a passivation layer that are disposed on a base substrate, the thin film transistor including a gate electrode, a gate insulation layer, an active layer, and source and drain electrodes,
wherein via holes in the planarization layer and the passivation layer in correspondence with the drain electrode are smoothly connected.

11 . The array substrate claimed as claim 10 , further comprising a pixel electrode layer disposed on the passivation layer and connected to the drain electrode and a pattern of a data line layer disposed on the base substrate, the base substrate including a display region and a peripheral region that adjoins and surrounds the display region, the pattern of the data line layer including a pattern of a data line provided in the display region and a lead pattern provided in the peripheral region, the lead pattern of the data line layer including a plurality of first leads arranged along a first direction and a plurality of second leads arranged along a second direction, and the first direction and the second direction being two different directions on a plane in parallel to the base substrate,
wherein between the first leads or the second leads of the data line layer, connection is realized by lead connection lines of the pixel electrode layer provided in the peripheral region.

12 . The array substrate claimed as claim 11 , wherein the pattern of the data line layer is disposed in the same layer as the source and drain electrodes.

13 . The array substrate claimed as claim 11 , wherein the pattern of the data line layer is disposed in the same layer as the gate electrode.

14 . A display panel, comprising the array substrate claimed as claim 10 .

15 . The method claimed as claim 2 , further comprising forming a pattern of a common electrode layer on the pattern of the planarization layer, wherein, forming of the patterns of the planarization layer and the passivation layer includes:
forming a thin film of a planarization layer material on the pattern of the thin film transistor; forming a thin film of a passivation layer material on the pattern of the common electrode layer; with one patterning process, forming the thin film of the planarization layer material to the pattern of the planarization layer, and forming the thin film of the passivation layer material to the pattern of the passivation layer.

16 . The method claimed as claim 15 , wherein forming of the patterns of the planarization layer and the passivation layer includes: forming a plurality of via holes in the thin film of the planarization layer material and the thin film of the passivation layer material.

17 . The method claimed as claim 15 , wherein forming of the thin film of the planarization layer material to a pattern of the planarization layer and the thin film of the passivation layer material to a pattern of the passivation layer with one patterning process includes:
coating a layer of photoresist on the substrate with the thin film of the planarization layer material and the thin film of the passivation layer formed thereon; conducting exposure of the photoresist with a mask, and then performing development on the exposed photoresist, so that a photoresist fully-retained region and a photoresist fully-removed region are formed after development, wherein the photoresist fully-removed region corresponds to region of the drain electrode, and a rest region is the photoresist fully-retained region; removing the thin film of the planarization layer material and the thin film of the passivation layer material provided in the photoresist fully-removed region; and removing the remaining

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Qu Lianjie

Classifications

• H10D84/01 Primary

  Manufacture or treatment · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title