Double-Sided Vertical Semiconductor Device With Thinned Substrate

Patent metadata

Field	Value
Publication number	US-2016358910-A1
Application number	US-201615240009-A
Country	US
Kind code	A1
Filing date	Aug 18, 2016
Priority date	Oct 12, 2010
Publication date	Dec 8, 2016
Grant date	—

Abstract

A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor layer having a front side and a back side, the semiconductor layer having background doping of a first conductivity type; a first doped region of a second conductivity type on the front side of the semiconductor layer; a second doped region of the first conductivity type, the second doped region being formed within the first doped region; a contact region of the second conductivity type, the contact region being adjacent to the second doped region and formed at the front side of the semiconductor layer; a dielectric layer formed on the front side of the semiconductor layer, the dielectric layer including a gate structure in electrical communication with the first doped region and a first electrical contact in communication with the second doped region and the contact region; an etched region on the back side of the semiconductor layer, the etched region including a third doped region having a larger lateral dimension than a lateral dimension of the first doped region; and a second electrical contact in communication with the third doped region.

2 . The semiconductor device of claim 1 , wherein the third doped region is of the second conductivity type, and wherein the semiconductor device comprises a thyristor.

3 . The semiconductor device of claim 1 , wherein the third doped region is of the first conductivity type.

4 . The semiconductor device of claim 3 , wherein the semiconductor device comprises an NPN bipolar device, and wherein the second electrical contact comprises a collector contact.

5 . The semiconductor device of claim 3 , wherein the semiconductor device comprises a Diffused Metal Oxide Semiconductor (DMOS) device, and wherein the second electrical contact comprises a drain contact.

6 . The semiconductor device of claim 3 , wherein the first electrical contact comprises a source contact.

7 . The semiconductor device of claim 1 , wherein the semiconductor device comprises a transistor.

8 . The semiconductor device of claim 1 , wherein the semiconductor layer comprises a buried oxide layer adjacent the etched region.

9 . The semiconductor device of claim 1 , wherein the first and second electrical contacts comprise metal.

10 . The semiconductor device of claim 1 , wherein the semiconductor device comprises an Insulated Gate Bipolar Transistor (IGBT), further wherein the first electrical contact shorts the second doped region and the first doped region.

11 . A vertical device comprising:
a semiconductor layer having a first surface on a back side, a second surface on a front side, a background doped region doped to a first conductivity type, and an etched portion of the back side exposing a third surface; the semiconductor layer comprising:
a first doped region, adjacent to the second surface, of a second conductivity type;
a second doped region of the first conductivity type, the second doped region being adjacent to the second surface and formed inside the first doped region, and
a contact region of the second conductivity type within the first doped region and adjacent the second doped region; and
a third doped region on the third surface, the third doped region having the first conductivity type;
a first electrical contact to the second doped region and the contact region at the second surface; and a second electrical contact to the third doped region on the third surface.

12 . The vertical device of claim 11 , wherein the third doped region has the first conductivity type.

13 . The vertical device of claim 12 , wherein the background doped region is doped uniformly to a first doping concentration, and wherein the third doped region has a peak doping concentration greater than ten times the first doping concentration.

14 . The vertical device of claim 12 , comprising an NPN bipolar device, and wherein the second electrical contact comprises a collector contact.

15 . The vertical device of claim 12 , comprising a Diffused Metal Oxide Semiconductor (DMOS) device, and wherein the second electrical contact comprises a drain contact.

16 . The vertical device of claim 12 , wherein the first electrical contact comprises a source contact.

17 . The vertical device of claim 11 , wherein the third doped region has the second conductivity type, and wherein the semiconductor device comprises a thyristor.

18 . The vertical device of claim 11 , wherein the third doped region has a doping concentration greater than 10 18 cm-3.

19 . The vertical device of claim 11 , further comprising an interconnect layer coupled to the second surface of the semiconductor layer, wherein the first electrical contact extends from the second surface of the semiconductor layer through the interconnect layer.

20 . The vertical device of claim 19 , further comprising a handle layer coupled to the interconnect layer.

21 . The vertical device of claim 11 , comprising an Insulated Gate Bipolar Transistor (IGBT), wherein the first electrical contact shorts the second doped region and the contact region.

22 . The vertical device of claim 11 , wherein the semiconductor layer comprises:
an insulator layer having a first surface, a second surface, and an etched portion; a semiconductor-on-insulator layer having a first surface and a second surface, the first surface contacting the first surface of the insulator layer, the second surface corresponding to the second surface of the semiconductor layer, and a portion of the first surface exposed by the etched portion of the insulator layer corresponding to the third surface of the semiconductor layer; and a substrate layer having a first surface, a second surface, and an etched portion, the second surface contacting the second surface of the insulator layer, the first surface corresponding to the first surface of the semiconductor layer.

23 . A transistor comprising:
a semiconductor layer having a front side and a back side, the semiconductor layer having background doping of a first conductivity type; the semiconductor layer including:
a first doped region of a second conductivity type on the front side of the semiconductor layer;
a second doped region of the first conductivity type, the second doped region being formed within the first doped region;
a contact region of the second conductivity type, the contact region being adjacent to the second doped region and formed at the front side of the semiconductor layer; and
an etched region on the back side of the semiconductor layer, the etched region including a third doped region; and
a drain electrical contact in communication with the third doped region; and a dielectric layer formed on the front side of the semiconductor layer, the dielectric layer including a gate structure in electrical communication with the first doped region and a source electrical contact in communication with the second doped region and the contact region.

24 . The transistor of claim 23 , wherein the third doped region has the first conductivity type.

25 . The transistor of claim 23 , wherein the third doped region has the second conductivity type.

26 . The transistor of claim 23 , wherein the source contact shorts the second doped region and the first doped region.

27 . The transistor of claim 23 , further comprising an interconnect layer coupled to the front side of the semicond

Assignees

• Qualcomm Inc

Inventors

• Stuber Michael Andrew
• Molin Stuart

Classifications

• H10W72/50

  Bond wires · CPC title

• H10W72/07551

  characterised by changes in properties of the bond wires during the connecting · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title