Methods of forming v0 structures for semiconductor devices by forming a protection layer with a non-uniform thickness

Patent metadata

Field	Value
Publication number	US-2016358908-A1
Application number	US-201514732038-A
Country	US
Kind code	A1
Filing date	Jun 5, 2015
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate structures, forming a non-uniform thickness layer of material on the upper surface of the gate cap layers and on the upper surface of the source/drain contact structure, wherein the non-uniform thickness layer of material is thicker above the gate cap layers than it is above the source/drain contact structure, forming an opening in the non-uniform thickness layer of material so as to expose at least a portion of the source/drain contact structure, and forming a V0 via that is conductively coupled to the exposed portion of the source/drain contact structure, the V0 via being at least partially positioned in the opening in the non-uniform thickness layer of material.

First claim

What is claimed:

1 . A method of forming a V0 via on an integrated circuit product comprised of two spaced-apart transistor gate structures, each of said gate structures having a gate cap layer, the method comprising:
forming a source/drain contact structure between said two spaced-apart transistor gate structures, wherein an upper surface of said source/drain contact structure is substantially planar with an upper surface of each of said gate cap layers; performing a deposition process to form a non-uniform thickness layer of material on said upper surface of said gate cap layers and on said upper surface of said source/drain contact structure, wherein portions of said non-uniform thickness layer of material positioned on said gate cap layers have a first thickness and a portion of said non-uniform thickness layer of material positioned on said source/drain contact structure has a second thickness that is substantially less than said first thickness; forming a first layer of insulating material above said non-uniform thickness layer of material; performing at least one etching process to form an opening in said non-uniform thickness layer of material so as to expose at least a portion of said source/drain contact structure; and forming said V0 via such that it is conductively coupled to said exposed portion of said source/drain contact structure, said V0 via being at least partially positioned in said opening in said non-uniform thickness layer of material.

2 . The method of claim 1 , wherein forming said source/drain contact structure comprises:
forming a line-type trench silicide contact that is conductively coupled to a source/drain region positioned between said two gate structures; and forming a line-type CA contact structure comprised of tungsten on said line-type trench silicide contact, wherein said upper surface of said contact structure is an upper surface of said line-type CA contact structure.

3 . The method of claim 1 , wherein forming said source/drain contact structure comprises forming said source/drain contact structure such that an upper portion of said source/drain contact structure is comprised of tungsten.

4 . The method of claim 1 , wherein performing said deposition process to form said non-uniform thickness layer of material comprises performing said deposition process such that said first thickness is at least 10-30 nm greater than said second thickness.

5 . The method of claim 1 , wherein performing said deposition process to form said non-uniform thickness layer of material comprises performing said deposition process such that said first thickness falls within a range of about 15-55 nm, while said second thickness falls within a range of about 5-25 nm.

6 . The method of claim 1 , wherein performing said deposition process to form said non-uniform thickness layer of material comprises performing a TELOS deposition process to form said non-uniform thickness layer of material.

7 . The method of claim 1 , wherein said two gate structures are each a replacement gate structure comprised of a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal.

8 . The method of claim 1 , wherein, after forming said first layer of insulating material and prior to performing said at least one etching process, the method further comprises forming an opening in said first layer of insulating material so as to expose a portion of said non-uniform thickness layer of material.

9 . The method of claim 1 , wherein forming said V0 via comprises forming said V0 via such that a portion of said V0 via is positioned vertically above said gate cap layer of at least one of said two gate structures and above a portion of said patterned non-uniform thickness layer of material.

10 . A method of forming a V0 via on an integrated circuit product comprised of two spaced-apart transistor gate structures, each of said gate structures having a gate cap layer, the method comprising:
forming a line-type trench silicide contact that is conductively coupled to a source/drain region positioned between said two gate structures; forming a line-type CA contact structure comprised of tungsten on said line-type trench silicide contact, wherein an upper surface of said line-type CA contact structure is substantially planar with an upper surface of each of said gate cap layers; performing a deposition process to form a non-uniform thickness layer of material on said upper surface of said gate cap layers and on said upper surface of said line-type CA contact structure, wherein portions of said non-uniform thickness layer of material positioned on said gate cap layers have a first thickness and a portion of said non-uniform thickness layer of material positioned on said line-type CA contact structure has a second thickness, said first thickness being at least 10-30 nm greater than said second thickness; forming a first layer of insulating material above said non-uniform thickness layer of material; performing at least one etching process to form an opening in said non-uniform thickness layer of material so as to expose at least a portion of said line-type CA contact structure; and forming said V0 via such that it is conductively coupled to said exposed portion of said line-type CA contact structure, said V0 via being at least partially positioned in said opening in said non-uniform thickness layer of material.

11 . The method of claim 10 , wherein performing said deposition process to form said non-uniform thickness layer of material comprises performing said deposition process such that said first thickness falls within a range of about 15-55 nm, while said second thickness falls within a range of about 5-25 nm.

12 . The method of claim 10 , wherein performing said deposition process to form said non-uniform thickness layer of material comprises performing a TELOS deposition process to form said non-uniform thickness layer of material.

13 . The method of claim 10 , wherein, after forming said first layer of insulating material and prior to performing said at least one etching process, the method further comprises forming an opening in said first layer of insulating material so as to expose a portion of said non-uniform thickness layer of material.

14 . The method of claim 10 , wherein forming said V0 via comprises forming said V0 via such that a portion of said V0 via is positioned vertically above said gate cap layer of at least one of said two gate structures and above a portion of said patterned non-uniform thickness layer of material.

15 . An integrated circuit product, comprising:
a plurality of spaced-apart transistor gate structures, each of said gate structures having a gate cap layer; a plurality of source/drain regions, wherein each of said source/drain regions is positioned between two adjacent gate structures; a plurality of source/drain contact structures, each of which is conductively coupled to one of said source/drain regions, wherein upper surfaces of said source/drain contact structures are substantially planar with upper surfaces of said gate cap layers; a non-uniform thickness layer of material positioned on said upper surfaces of said gate cap layers and on said upper surfaces of said source/drain contact structures, wherein portions of said non-uniform thickness layer of material positioned on said gate cap layers have a first thickness and portions of said non-uniform thickness layer of material positioned on said source/drain contact structures have a second thickness that is substantially less than said first thicknes

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Zhang Xunyuan

Classifications

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D30/0212

  using self-aligned silicidation · CPC title