Arrangement of multiple power semiconductor chips and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016358886-A1
Application number	US-201615171364-A
Country	US
Kind code	A1
Filing date	Jun 2, 2016
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.

First claim

What is claimed is:

1 . A semiconductor power arrangement, comprising:
a chip carrier having a first surface and a second surface opposite the first surface; and a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.

2 . The semiconductor power arrangement of claim 1 , wherein the power semiconductor chips are perpendicular to the first and/or second surface of the chip carrier.

3 . The semiconductor power arrangement of claim 1 , wherein the power semiconductor chips are oriented parallel to each other, and wherein a distance between adjacent power semiconductor chips is equal to or less than 4.0 mm, 3.0 mm, 2.0 mm, 1.5 mm, 1.0 mm, 0.75 mm, 0.5 mm, or 0.3 mm.

4 . The semiconductor power arrangement of claim 1 , wherein the chip carrier has a plurality of through-holes or slits and the power semiconductor chips pass through the through-holes or slits.

5 . The semiconductor power arrangement of claim 1 , wherein edges of the power semiconductor chips are mounted on at least one of the first surface and the second surface of the chip carrier.

6 . The semiconductor power arrangement of claim 1 , wherein at least one of the first surface and the second surface is provided with a plurality of trenches, and wherein edges of the power semiconductor chips are inserted into the trenches.

7 . The semiconductor power arrangement of claim 1 , wherein the power semiconductor chips are bonded to the chip carrier by a soldering material, a sintering material or a plating material.

8 . The semiconductor power arrangement of claim 1 , wherein the power semiconductor chips are bare chips.

9 . The semiconductor power arrangement of claim 1 , wherein the power semiconductor chips comprise electrodes, wherein the electrodes are connected to the chip carrier either directly or via metal traces running over the power semiconductor chips.

10 . The semiconductor power arrangement of claim 1 , wherein the power semiconductor chips are each attached to at least one of a first side and/or a second side metal foil.

11 . The semiconductor power arrangement of claim 10 , wherein the first side metal foil and/or the second side metal foil are fixed to the chip carrier.

12 . The semiconductor power arrangement of claim 10 , wherein the first side metal foil and/or the second side metal foil are configured to hold the power semiconductor chip in place.

13 . The semiconductor power arrangement of claim 10 , wherein the first side metal foil and/or the second side metal foil pass through a through-hole or slit in the chip carrier.

14 . The semiconductor power arrangement of claim 1 , wherein the chip carrier comprises a PCB, a ceramic plate covered by a structured metallization to form the first and second surfaces thereof, a leadframe, an isolated metal substrate, or a molded interconnect substrate.

15 . The semiconductor power arrangement of claim 1 , wherein the chip carrier comprises an electrical wiring and an electrical connector which is electrically connected to the electrical wiring.

16 . The semiconductor power arrangement of claim 1 , further comprising:
a container configured to accommodate the chip carrier and the plurality of power semiconductor chips.

17 . A semiconductor power module, comprising:
a chip carrier having a first surface and a second surface opposite the first surface; a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier; a container configured to accommodate the chip carrier and the plurality of power semiconductor chips; and a cooling fluid provided in the container, wherein the plurality of the power semiconductor chips are submerged in the cooling fluid.

18 . The semiconductor power module of claim 17 , wherein the power semiconductor chips are perpendicular to the first and/or second surface of the chip carrier.

19 . The semiconductor power module of claim 17 , wherein the power semiconductor chips are oriented parallel to each other, and wherein a distance between adjacent power semiconductor chips is equal to or less than 4.0 mm.

20 . A method of manufacturing a semiconductor power arrangement, the method comprising:
defining a chip carrier to have a first surface and a second surface opposite the first surface; and attaching a plurality of power semiconductor chips to a chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.

21 . The method of claim 20 , wherein the power semiconductor chips are arranged perpendicular to the first and/or second surface of the chip carrier.

22 . The method of claim 20 , further comprising:
inserting the power semiconductor chips through through-holes or into slits in the chip carrier.

23 . The method of claim 20 , further comprising:
inserting edges of the power semiconductor chips into trenches provided in at least one of the first surface and the second surface of the chip carrier.

24 . The method of claim 20 , further comprising:
attaching each of the power semiconductor chips to at least one of a first side metal foil and/or a second side metal foil; and fixing the first side metal foil and/or the second side metal foil to the chip carrier.

Assignees

• Infineon Technologies Ag

Inventors

• Meyer-Berg Georg
• Fuergut Edward
• Mahler Joachim

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title