Nonvolatile memory device and program method thereof

Patent metadata

Field	Value
Publication number	US-2016358657-A1
Application number	US-201615083834-A
Country	US
Kind code	A1
Filing date	Mar 29, 2016
Priority date	Jun 8, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile memory devices through one channel. During a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel. While the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.

First claim

What is claimed is:

1 . A nonvolatile memory system comprising:
first and second nonvolatile memory devices; and a memory controller configured to control the first and second nonvolatile memory devices through one channel, wherein: during a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel, and while the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.

2 . The nonvolatile memory system of claim 1 , wherein:
the memory controller transmits a first chip enable signal to the first nonvolatile memory device, a second chip enable signal to the second nonvolatile memory device, and data signals and control signals to the first and second nonvolatile memory devices, the first nonvolatile memory device transmits a first ready/busy signal to the memory controller, and the second nonvolatile memory device transmits a second ready/busy signal to the memory controller.

3 . The nonvolatile memory system of claim 2 , wherein the memory controller transmits the first signals to the first nonvolatile memory device by activating the first chip enable signal and transmits the second signals to the second nonvolatile memory device by activating the second chip enable signal.

4 . The nonvolatile memory system of claim 2 , wherein the first ready/busy signal remains at a busy state while the first nonvolatile memory device sets up the first page data in response to the first signals.

5 . The nonvolatile memory system of claim 1 , wherein the first signals comprise a first command set, a first address, and the first page data and the second signals comprises a second command set, a second address, and the second page data.

6 . The nonvolatile memory system of claim 5 , wherein:
each of the first and second command sets comprises a program start command, a dump command, and a dump appointment command, and the first address and the second address indicate a physical location where the first page data is to be written and a physical location where the second page data is to be written, respectively.

7 . The nonvolatile memory system of claim 1 , wherein:
while the second nonvolatile memory device sets up the second page data in response to the second signals, the memory controller transmits third signals, for setting third page data up in the first nonvolatile memory device, to the first nonvolatile memory device, while the first nonvolatile memory device sets up the third page data in response to the third signals, the memory controller transmits fourth signals, for setting fourth page data up in the second nonvolatile memory device, to the second nonvolatile memory device, and while the second nonvolatile memory device sets up the fourth page data in response to the fourth signals, the memory controller transmits fifth signals, for setting fifth page data up in the first nonvolatile memory device, to the first nonvolatile memory device.

8 . The nonvolatile memory system of claim 7 , wherein:
after the first nonvolatile memory device sets up the fifth page data in response to the fifth signals, the memory controller transmits a program confirm command to the first nonvolatile memory device, and the first nonvolatile memory device performs a program operation of the first, third, and fifth page data in response to the program confirm command.

9 . The nonvolatile memory system of claim 1 , wherein:
each of the first and second nonvolatile memory devices comprises a page buffer circuit, and each of the first and second nonvolatile memory devices sets the first and second page data up in the page buffer circuit.

10 . The nonvolatile memory system of claim 1 , wherein each of the first and second nonvolatile memory devices comprises a three-dimensional cell array.

11 . A program method of a nonvolatile memory system which comprises first and second nonvolatile memory devices and a memory controller controlling the first and second nonvolatile memory devices through a channel, the method comprising:
setting first page data up in the first nonvolatile memory device; setting second page data up in the second nonvolatile memory device; setting third page data up in the first nonvolatile memory device; setting fourth page data up in the second nonvolatile memory device; setting fifth page data up in the first nonvolatile memory device; performing a program operation of the first nonvolatile memory device after the fifth page data is set up in the first nonvolatile memory device; setting sixth page data up in the second nonvolatile memory device; and performing a program operation of the second nonvolatile memory device after the sixth page data is set up in the second nonvolatile memory device.

12 . The method of claim 11 , further comprising:
transmitting a program confirm command to the first nonvolatile memory device after the setting of the fifth page data, wherein a first chip enable signal of the first nonvolatile memory device remains at an active state while the setting of the first page data, the setting of the third page data, the setting of the fifth page data, and the transmitting of the program confirm command are performed.

13 . The method of claim 11 , further comprising:
transmitting a program confirm command to the second nonvolatile memory device after the setting of the sixth page data, wherein a second chip enable signal of the second nonvolatile memory device remains at an active state while the setting of the second page data, the setting of the fourth page data, the setting of the sixth page data, and the transmitting of the program confirm command are performed.

14 . The method of claim 11 , wherein a first ready/busy signal from the first nonvolatile memory device remains at a busy state during a time, when the setting of the first page data is performed.

15 . The method of claim 11 , wherein:
the performing of the program operation of the first nonvolatile memory device comprises programming the first, third, and fifth page data at the first nonvolatile memory device, and the performing of the program operation of the second nonvolatile memory device comprises programming the second, fourth, and sixth data at the second nonvolatile memory device.

16 . A nonvolatile memory system comprising:
first and second nonvolatile memory devices, the first nonvolatile memory device comprising a first memory cell array, a first control circuit, and a first page buffer and the second nonvolatile memory device comprising a second memory cell array, a second control circuit, and a second page buffer; and a memory controller that communicates through the communication channel:
first page data, a first address where the first page data is to be stored, and a first program command to the first control circuit of the first nonvolatile memory device, and
second page data, a second address where the second page data is to be stored, and a second program command to the second control circuit of the second nonvolatile memory device while the first control circuit of the first nonvolatile memory device stores the first page data in the first page buffer.

17 . The nonvolatile memory system of claim 16 , wherein the memory controller further communicates through the communication ch

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jinwoo
• Kim Seong Yeon
• Park Jaegeun
• Shin Hyo-Deok
• Lee Younggeun
• Cho Youngjin

Classifications

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title