Automated conversion of gpgpu workloads to 3d pipeline workloads

Patent metadata

Field	Value
Publication number	US-2016358300-A1
Application number	US-201514729915-A
Country	US
Kind code	A1
Filing date	Jun 3, 2015
Priority date	Jun 3, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

Systems, apparatuses and methods may provide for receiving a general purpose graphics processing unit (GPGPU) workload and converting the GPGPU workload to a three-dimensional (3D) workload. Additionally, the 3D workload may be dispatched to a 3D pipeline. In one example, converting the GPGPU workload to the 3D workload includes identifying a plurality of thread groups in the GPGPU workload and mapping the plurality of thread groups to a 3D matrix of cubes.

First claim

We claim:

1 . A computing device comprising:
a host processor including a workload converter to convert a general purpose graphics processing unit (GPGPU) workload to a three-dimensional (3D) workload; a graphics processor including:
a 3D pipeline, and
a command streamer to dispatch the 3D workload to the 3D pipeline.
a display interface to receive data associated with an execution of the 3D workload; and a display device to generate a display output based on the data in the display interface.

2 . The computing device of claim 1 , wherein the workload converter is to identify a plurality of thread groups in the GPGPU workload and map the plurality of thread groups to a 3D matrix of cubes.

3 . The computing device of claim 2 , wherein each cube is to represent an array of two-dimensional (2D) primitives.

4 . The computing device of claim 3 , wherein each primitive is to be a quad.

5 . The computing device of claim 1 , wherein the 3D pipeline includes:
a pixel shader interface; and a vertex shader to identify, for each of a plurality of two-dimensional (2D) primitives associated with the 3D workload, a plurality of vertices and generate system values for the plurality of vertices, wherein the system values are to have a one-to-one relationship with the pixel shader interface.

6 . The computing device of claim 1 , wherein the command streamer is to call a plurality of non-GPGPU shader threads to dispatch the 3D workload.

7 . A computing architecture comprising:
a workload converter to receive a general purpose graphics processing unit (GPGPU) workload and convert the GPGPU workload to a three-dimensional (3D) workload; a 3D pipeline; and a command streamer to dispatch the 3D workload to the 3D pipeline.

8 . The computing architecture of claim 7 , wherein the workload converter is to identify a plurality of thread groups in the GPGPU workload and map the plurality of thread groups to a 3D matrix of cubes.

9 . The computing architecture of claim 8 , wherein each cube is to represent an array of two-dimensional (2D) primitives.

10 . The computing architecture of claim 9 , wherein each primitive is to be a quad.

11 . The computing architecture of claim 7 , wherein the 3D pipeline includes:
a pixel shader interface; and a vertex shader to identify, for each of a plurality of two-dimensional (2D) primitives associated with the 3D workload, a plurality of vertices and generate system values for the plurality of vertices, wherein the system values are to have a one-to-one relationship with the pixel shader interface.

12 . The computing architecture of claim 7 , wherein the command streamer is to call a plurality of non-GPGPU shader threads to dispatch the 3D workload.

13 . A method comprising:
receiving a general purpose graphics processing unit (GPGPU) workload; converting the GPGPU workload to a three-dimensional (3D) workload; and dispatching the 3D workload to a 3D pipeline.

14 . The method of claim 13 , wherein converting the GPGPU workload to the 3D workload includes:
identifying a plurality of thread groups in the GPGPU workload; and mapping the plurality of thread groups to a 3D matrix of cubes.

15 . The method of claim 14 , wherein each cube represents an array of two-dimensional (2D) primitives.

16 . The method of claim 15 , wherein each 2D primitive is a quad.

17 . The method of claim 13 , further including:
identifying, for each of a plurality of two-dimensional (2D) primitives associated with the 3D workload, a plurality of vertices; and generating system values for the plurality of vertices, wherein the system values have a one-to-one relationship with a pixel shader interface associated with the 3D pipeline.

18 . The method of claim 13 , wherein dispatching the 3D workload to the 3D pipeline includes calling a plurality of non-GPGPU shader threads.

19 . At least one computer readable storage medium comprising a set of instructions, which when executed by a computing device, cause the computing device to:
receive a general purpose graphics processing unit (GPGPU) workload; convert the GPGPU workload to a three-dimensional (3D) workload; and dispatch the 3D workload to a 3D pipeline.

20 . The at least one computer readable storage medium of claim 19 , wherein the instructions, when executed, cause the computing device to:
identify a plurality of thread groups in the GPGPU workload; and map the plurality of thread groups to a 3D matrix of cubes to convert the GPGPU workload to the 3D workload.

21 . The at least one computer readable storage medium of claim 20 , wherein each cube is to represent an array of two-dimensional (2D) primitives.

22 . The at least one computer readable storage medium of claim 21 , wherein each 2D primitive is to be a quad.

23 . The at least one computer readable storage medium of claim 19 , wherein the instructions, when executed, cause the computing device to:
identify, for each of a plurality of two-dimensional (2D) primitives associated with the 3D workload, a plurality of vertices; and generate system values for the plurality of vertices, wherein the system values are to have a one-to-one relationship with a pixel shader interface associated with the 3D pipeline.

24 . The at least one computer readable storage medium of claim 19 , wherein the instructions, when executed, cause the computing device to call a plurality of non-GPGPU shader threads to dispatch the 3D workload.

Assignees

• Intel Corp

Inventors

• Taylor Robert B
• Venkatesh Abhishek

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/5044

  considering hardware capabilities · CPC title

• G06F9/48

  Program initiating; Program switching, e.g. by interrupt · CPC title