Signal conditioner for high-speed data communications

Patent metadata

Field	Value
Publication number	US-2016357699-A1
Application number	US-201514731378-A
Country	US
Kind code	A1
Filing date	Jun 4, 2015
Priority date	Jun 4, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A method, signal conditioning circuit, and system are disclosed to perform signal conditioning using a processing component coupled with at least first and second inputs. The processing component is further coupled with a first output port including first and second data lanes operable at different data rates. The method includes receiving, via the first input and at a first data rate, data included in a first input signal, and receiving, via the second input and at a second data rate different from the first data rate, data included in a second input signal. The method further includes driving, based on the first and second input signals, a first output signal onto the first output port, which includes transmitting the data included in the first input signal on the first data lane, and transmitting the data included in the second input signal on the second data lane.

First claim

We claim:

1 . A signal conditioning circuit, comprising:
a first input configured to receive data included in a first input signal at a first data rate; a second input configured to receive data included in a second input signal at a second data rate different from the first data rate; and a processing component coupled with the first and second inputs and configured to drive a first output signal based on the first and second input signals onto a first output port including at least first and second data lanes operable at different data rates, wherein driving the first output signal comprises:
transmitting the data included in the first input signal on the first data lane; and
transmitting the data included in the second input signal on the second data lane.

2 . The signal conditioning circuit of claim 1 , wherein the processing component comprises one of retimer circuitry and re-driver circuitry for conditioning the received first and second input signals prior to driving the first output signal.

3 . The signal conditioning circuit of claim 1 , wherein the signal conditioning arrangement comprises a plurality of output ports including the first output port, and is configured to receive a plurality of input signals including the first and second input signals,
wherein the processing component comprises an allocation component configured to allocate, based on an analysis of the plurality of received input signals, each of the received input signals to a corresponding one of the plurality of output ports.

4 . The signal conditioning circuit of claim 3 , wherein the allocation component is further configured to determine a type of device connected with one or more of the plurality of output ports,
wherein the allocation of the received input signals to the plurality of output ports is further based on the determined type of the device.

5 . The signal conditioning circuit of claim 3 , wherein the allocation component is further configured to allocate each of the received input signals to one or more corresponding data lanes within the allocated output port.

6 . The signal conditioning circuit of claim 1 , wherein the first input and the second input correspond to different interfaces.

7 . The signal conditioning circuit of claim 6 , wherein the respective interfaces of the first input and the second input are each selected from a DisplayPort interface, a Universal Serial Bus (USB) interface, a USB Type-C interface, a Peripheral Component Interconnect Express (PCIe) interface, and a Thunderbolt interface.

8 . The signal conditioning circuit of claim 1 , wherein the processing component is further configured to receive data using the first and second data lanes.

9 . A method of signal conditioning using a processing component coupled with at least first and second inputs and further coupled with at least a first output port including first and second data lanes operable at different data rates, the method comprising:
receiving, via the first input and at a first data rate, data included in a first input signal; receiving, via the second input and at a second data rate different from the first data rate, data included in a second input signal; and driving, based on the first and second input signals, a first output signal onto the first output port, wherein driving the first output signal includes:
transmitting the data included in the first input signal on the first data lane; and
transmitting the data included in the second input signal on the second data lane.

10 . The method of claim 9 , wherein the processing component comprises one of retimer circuitry and re-driver circuitry for conditioning the received first and second input signals prior to driving the first output signal.

11 . The method of claim 9 , wherein the processing component is coupled with a plurality of output ports including the first output port, and is configured to receive a plurality of input signals including the first and second input signals, the method further comprising:
allocating, via the processing component and based on an analysis of the plurality of received input signals, each of the received input signals to a corresponding one of the plurality of output ports.

12 . The method of claim 11 , further comprising:
determining a type of device connected with one or more of the plurality of output ports, wherein the allocation of the received input signals to the plurality of output ports is further based on the determined type of the device.

13 . The method of claim 11 , wherein the allocation further includes allocating each of the received input signals to one or more corresponding data lanes within the allocated output port.

14 . The method of claim 9 , wherein the first input and the second input correspond to different interfaces.

15 . The method of claim 14 , wherein the respective interfaces of the first input and the second input are each selected from a DisplayPort interface, a Universal Serial Bus (USB) interface, a USB Type-C interface, a Peripheral Component Interconnect Express (PCIe) interface, and a Thunderbolt interface.

16 . The method of claim 9 , wherein the processing component is further configured to receive data using the first and second data lanes.

17 . A system, comprising:
one or more source devices configured to produce a first signal at a first data rate, and a second signal at a second data rate different from the first data rate; and a signal conditioning circuit including at least first and second inputs coupled with respective outputs of the one or more source devices, and further including at least a first output port, wherein the arrangement is configured to:
receive the produced first and second signals at the first and second inputs; and
drive a first output signal onto the first output port based on the received first and second signals, the first output port including at least first and second data lanes operable at different data rates, wherein driving the first output signal comprises:
transmitting the data included in the first input signal on the first data lane; and
transmitting the data included in the second input signal on the second data lane.

18 . The system of claim 17 , wherein the signal conditioning circuit comprises one of retimer circuitry and re-driver circuitry for conditioning the received first and second input signals prior to driving the first output signal.

19 . The system of claim 17 , wherein the signal conditioning circuit comprises a plurality of output ports including the first output port, and is configured to receive a plurality of input signals including the first and second input signals,
wherein the signal conditioning circuit is further configured to allocate, based on an analysis of the plurality of received input signals, each of the received input signals to a corresponding one of the plurality of output ports.

20 . The system of claim 17 , wherein the respective interfaces of the first input and the second input are each selected from a DisplayPort interface, a Universal Serial Bus (USB) interface, a USB Type-C interface, a Peripheral Component Interconnect Express (PCIe) interface, and a Thunderbolt interface.

Assignees

• Synaptics Inc

Inventors

• Shamarao Prashant
• Lukanc Jeffrey

Classifications

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/4018

  with data-width conversion · CPC title

• G06F13/20 Primary

  for access to input/output bus · CPC title