Distributed mechanism for clock and reset control in a microprocessor

Patent metadata

Field	Value
Publication number	US-2016357571-A1
Application number	US-201514731216-A
Country	US
Kind code	A1
Filing date	Jun 4, 2015
Priority date	Jun 4, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

Implementations of the present disclosure involve a system and/or method for implementing a reset controller of a microprocessor or other type of computing system by connecting the reset controller to a reset controller bus or other type of general purpose bus. Through the reset bus, the reset controller signals used to generate the reset sequence of the system may be transmitted to the components of the system through a bus, rather than utilizing a direct wire connection between the components and the reset controller. The wires that comprise the reset bus may then be run to one or more components of the microprocessor design that are restarted during the reset sequence. Each of these components may also include a reset controller circuit that is designed to receive the reset control signals from the reset controller and decode the signals to determine if the received signal applies to the component.

First claim

What is claimed is:

1 . A microelectronic circuit comprising:
a plurality of logic portions of the microelectronic circuit, each of the plurality of logic portions comprising at least one component configured to be resettable during a restart of the microelectronic circuit; a reset communication bus in electrical communication with each of the plurality of logic portions; and a reset controller electrically connected to the reset communication bus and configured to transmit one or more reset control messages comprising an address and a command on the reset communication bus and receive one or more response messages from the reset communication bus; wherein each of the plurality of logic portions receive each of the one or more reset control messages transmitted on the reset communication bus from the reset controller and each of the plurality of logic portions is configured to obtain the reset control message address of the received one or more reset control messages and execute the reset control message command.

2 . The microelectronic circuit of claim 1 wherein each of the plurality of logic portions further comprises an associated address and wherein a first logic portion of the plurality of logic portions executes the reset control message if the reset control message address matches the associated address for the first logic portion.

3 . The microelectronic circuit of claim 1 wherein the reset communication bus comprises a plurality of control message transmitters, a first valid signal transmitter, and a second valid signal transmitter.

4 . The microelectronic circuit of claim 3 wherein an asserted signal on the first valid signal transmitter of the reset communication bus indicates the presence of a valid reset control message on one or more of the plurality of control message transmitters.

5 . The microelectronic circuit of claim 3 wherein an asserted signal on the second valid signal transmitter of the reset communication bus indicates the presence of a valid response message on one or more of the plurality of control message transmitters.

6 . The microelectronic circuit of claim 5 wherein each of the plurality of logic portions of the microelectronic circuit is further configured to assert the second valid signal transmitter and transmit the response message on the one or more of the plurality of control message transmitters.

7 . The microelectronic circuit of claim 3 wherein the one or more reset control messages comprises a plurality of packets transmitted on the plurality of control message transmitters.

8 . The microelectronic circuit of claim 7 wherein the plurality of packets for a read reset control message comprises a plurality of address packets.

9 . The microelectronic circuit of claim 7 wherein the plurality of packets for a write reset control message comprises a plurality of address packets and a plurality of data packets.

10 . The microelectronic circuit of claim 1 wherein the reset communication bus comprises a ring structure around the plurality of logic portions of an outer portion of the microelectronic circuit.

11 . The microelectronic circuit of claim 10 wherein the reset communication bus further comprises a branch path through an interior portion of the microelectronic circuit.

12 . A method for resetting a microelectronic circuit comprising:
transmitting, from a reset controller, one or more reset control messages comprising an address and a command on a reset communication bus to a plurality of logic portions of the microelectronic circuit, wherein each of the plurality of logic portions is in electrical communication with the reset communication bus and comprises at least one component configured to be resettable during a restart of the microelectronic circuit; and receiving from the reset communication bus one or more response messages from the reset communication bus; wherein each of the plurality of logic portions receive each of the one or more reset control messages transmitted on the reset communication bus from the reset controller and each of the plurality of logic portions is configured to obtain the reset control message address of the received one or more reset control messages and execute the reset control message command.

13 . The method of claim 12 wherein each of the plurality of logic portions further comprises an associated address and wherein a first logic portion of the plurality of logic portions executes the reset control message if the reset control message address matches the associated address for the first logic portion.

14 . The method of claim 12 wherein the reset communication bus comprises a plurality of control message transmitters, a first valid signal transmitter, and a second valid signal transmitter.

15 . The method of claim 14 further comprising asserting a signal on the first valid signal transmitter of the reset communication bus to indicate the presence of a valid reset control message on one or more of the plurality of control message transmitters.

16 . The method of claim 14 further comprising asserting a signal on the second valid signal transmitter of the reset communication bus to indicate the presence of a valid response message on one or more of the plurality of control message transmitters.

17 . The method of claim 16 wherein each of the plurality of logic portions of the microelectronic circuit is further configured to assert the second valid signal transmitter and transmit the response message on the one or more of the plurality of control message transmitters.

18 . The method of claim 14 wherein the one or more reset control messages comprises a plurality of packets transmitted on the plurality of control message transmitters.

19 . The method of claim 18 wherein the plurality of packets for a read reset control message comprises a plurality of address packets.

20 . The method of claim 18 wherein the plurality of packets for a write reset control message comprises a plurality of address packets and a plurality of data packets.

Assignees

• Oracle Int Corp

Inventors

• Vahidsafa Ali

Classifications

• G06F13/362 Primary

  with centralised access control · CPC title

• G06F9/4401 Primary

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title