Calibrating charge mismatch in a baseline correction circuit

Patent metadata

Field	Value
Publication number	US-2016357299-A1
Application number	US-201514731385-A
Country	US
Kind code	A1
Filing date	Jun 4, 2015
Priority date	Jun 4, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

Various embodiments provide a processing module that calibrates a current-mode baseline correction system to account for features in an input device that lead to “offset” in output of a charge integrator used for sensing presence of an input object. The offset is a difference between a common mode voltage, which is the average voltage output of the charge integrator over a sensing cycle and a mid-rail voltage midway between high and low power supply voltages. Calibration is performed by adjusting an N-side and/or P-side current flow duration parameter until common mode voltage falls within a low offset window in which the offset is deemed to be sufficiently close to the mid-rail voltage. The resulting duration parameters are stored and used for current-mode baseline corrections when operating an associated sensor electrode for capacitive sensing.

First claim

What is claimed is:

1 . A processing system for calibrating current-mode baseline operations, the processing system comprising:
a charge integrator coupled to a sensor electrode configured to be driven with a sensing signal for capacitive sensing; a baseline unit configured to flow first current to the charge integrator for a first duration during a first period of a cycle of the sensing signal and to flow second current to the charge integrator for a second duration during a second period of the cycle of the sensing signal; and a calibration unit configured to determine values for one or more of the first duration and the second duration at which a common mode voltage of the charge integrator is within a prescribed range.

2 . The processing system of claim 1 , wherein the calibration unit is configured to determine the values for the first duration and the second duration by:
for each cycle of a plurality of cycles in which the sensor electrode is driven for capacitive sensing, varying one or more of the first duration and the second duration; and identifying the combination of first duration and second duration for which the common mode voltage is within the prescribed range.

3 . The processing system of claim 2 , wherein the calibration unit is configured to vary either of the first duration during the first period of the cycle or the second duration during the second period of the cycle.

4 . The processing system of claim 2 further comprising:
a signal generator configured to drive the sensor electrode for capacitive sensing a number of times for each combination of first duration and second duration, wherein the calibration unit is further configured to determine the values for the first duration and the second duration by:
for each cycle of the plurality of cycles, recording a count of a number of times that the common mode voltage is not within the prescribed range, and
identifying a combination of first duration and second duration for which an associated count of the number of times that the common mode voltage is not within the prescribed range is lower than for any other combination of first duration and second duration.

5 . The processing system of claim 1 , wherein the baseline unit comprises:
a current mirror including a first switchable current channel configured to flow the first current to the charge integrator when activated; and a second switchable current channel configured to flow the second current the charge integrator when activated.

6 . The processing system of claim 5 , wherein the baseline unit further comprises:
a current conveyor configured to generate a reference current, wherein the first current and the second current are based on the reference current.

7 . The processing system of claim 5 , wherein:
the first switchable current channel includes an N-type metal-oxide-semiconductor (NMOS) transistor and a first switch; and the second switchable current channel includes a P-type metal-oxide-semiconductor (PMOS) transistor and a second switch.

8 . The processing system of claim 1 , wherein:
the calibration unit is configured to determine the common mode voltage by:
sampling an output of the charge integrator during the first period to determine a first sample;
sampling the output of the charge integrator during the second period to determine a second sample; and
calculating the common mode voltage based on averaging the first sample and the second sample.

9 . The processing system of claim 1 further comprising:
a second charge integrator coupled to a second sensor electrode configured to be driven with a second sensing signal for capacitive sensing; and
a second baseline unit configured to flow third current to the second charge integrator for the first duration during a first period of a cycle of the second sensing signal and to flow a fourth current to the second charge integrator for the second duration during a second portion of the cycle of the second sensing signal,
wherein the calibration unit is configured to determine values for the first duration and the second duration based on a common mode voltage of the second charge integrator and the common mode voltage of the first charge integrator.

10 . A method for calibrating current-mode baseline operations, the method comprising:
driving a sensor electrode coupled to a charge integrator with a signal; flowing first current to the charge integrator for a first duration during a first period of a cycle of the sensing signal; flowing second current to the charge integrator for a second duration during a second period of the cycle of the sensing signal; and determining values for one or more of the first duration and the second duration at which a common mode voltage of the charge integrator is within a prescribed range.

11 . The method of claim 10 , wherein determining the values for the first duration and the second duration comprises:
for each cycle of a plurality of cycles in which the sensor electrode is driven for capacitive sensing, varying one or more of the first duration and the second duration; and identifying the combination of first duration and second duration for which the common mode voltage is within the prescribed range.

12 . The method of claim 11 , further comprising varying either of the first duration during the first period of the cycle or the second duration during the second period of the cycle.

13 . The processing system of claim 11 further comprising:
driving the sensor electrode for capacitive sensing a number of times for each combination of first duration and second duration,
wherein determining the values for the first duration and the second duration comprises:
for each cycle of the plurality of cycles, recording a count of a number of times that the common mode voltage is not within the prescribed range, and
identifying a combination of first duration and second duration for which an associated count of the number of times that the common mode voltage is not within the prescribed range is lower than for any other combination of first duration and second duration.

14 . The method of claim 10 , wherein:
flowing the first current comprises activating a first switchable current channel of a current mirror to flow the first current to the charge integrator; and flowing the second current comprises activating a second switchable current channel of the current mirror to flow the second current to the charge integrator.

15 . The method of claim 14 , wherein:
the first current and the second current are based on a reference current generated by a current conveyor.

16 . The method of claim 14 , wherein:
flowing the first current further comprises activating an N-type metal-oxide-semiconductor (NMOS) transistor and a first switch; and flowing the second current further comprises activating a P-type metal-oxide-semiconductor (PMOS) transistor and a second switch.

17 . The method of claim 10 , further comprising:
determining the common mode voltage by:
sampling an output of the charge integrator during the first period to determine a first sample;
sampling the output of the charge integrator during the second period to determine a second sample; and
calculating the common mode voltage based on averaging the first sample and the second sample.

18 . The method of claim 10 further comprising:
driving a second sensor electrode coupled to a second charge integrator with a second signal;
flowing third current to the second charge integrator for the first

Assignees

• Synaptics Inc

Inventors

• Liu Chunbo
• Betancourt Rafael
• Chung Tae-Song
• Lo Steve Chikin

Classifications

• G06F2203/04108

  Touchless 2D- digitiser, i.e. digitiser detecting the X/Y position of the input means, finger or stylus, also when it does not touch, but is proximate to the digitiser's interaction surface without distance measurement in the Z direction · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title

• G06F3/0443

  using a single layer of sensing electrodes · CPC title