Array Substrate And Manufacturing Method For The Same, And Totally Reflective Type Liquid Crystal Display

Patent metadata

Field	Value
Publication number	US-2016357044-A1
Application number	US-201514891729-A
Country	US
Kind code	A1
Filing date	May 22, 2015
Priority date	Dec 10, 2014
Publication date	Dec 8, 2016
Grant date	—

Abstract

The present disclosure discloses an array substrate, comprising a substrate, a plurality of pixel regions on the substrate, and a thin-film transistor formed in each of the pixel regions, each of the pixel regions comprising a pixel electrode region, wherein, the thin-film transistor comprises a gate layer and a source/drain layer formed laminatedly on the substrate; the array substrate further comprises a flat layer and a reflective metal layer formed in sequence on the substrate and covering at least the pixel electrode region and the thin-film transistor; the reflective metal layer is electrically connected to a drain of the thin-film transistor; and at least one of the gate layer and the source/drain layer is formed of a single metal layer. The present disclosure further provides a method for manufacturing the array substrate and a totally reflective type liquid crystal display comprising the array substrate.

First claim

1 . An array substrate, comprising a substrate, a plurality of pixel regions on the substrate, and a thin-film transistor formed in each of the pixel regions, each of the pixel regions comprising a pixel electrode region, wherein,
the thin-film transistor comprises a gate layer and a source/drain layer formed laminatedly on the substrate; the array substrate further comprises a flat layer and a reflective metal layer formed in sequence on the substrate and covering at least the pixel electrode region and the thin-film transistor; the reflective metal layer is electrically connected to a drain of the thin-film transistor; and at least one of the gate layer and the source/drain layer is formed of a single metal layer.

2 . The array substrate of claim 1 , wherein the gate layer and the source/drain layer both are formed of a single metal layer.

3 . The array substrate of claim 2 , wherein the gate layer and the source/drain layer are formed of one and the same metal.

4 . The array substrate of claim 3 , wherein the gate layer and the source/drain layer have the same thickness.

5 . The array substrate of claim 3 , wherein the metal comprises one of molybdenum, copper and aluminum.

6 . The array substrate of claim 4 , wherein the gate layer and the source/drain layer both are formed of a molybdenum layer with a thickness of 2200 Å.

7 . The array substrate of claim 1 , wherein a portion of the reflective metal layer covering the pixel electrode region is substantially flat, and the reflective metal layer is formed of one of Al, Ag and AlNd.

8 . (canceled)

9 . The array substrate of claim 1 , wherein the flat layer comprises a resin layer.

10 . The array substrate of claim 1 , further comprising a surrounding lead wire region, wherein
the reflective metal layer is further formed on the surrounding lead wire region; and a portion of the reflective metal layer located on the surrounding lead wire region is covered with an indium tin oxide layer.

11 . A totally reflective type liquid crystal display, comprising an array substrate of claim 1 .

12 . A method for manufacturing an array substrate, comprising:
providing a substrate comprising a plurality of pixel regions which is to form a plurality of pixels, each of the pixel regions comprising a pixel electrode region which is to form a pixel electrode; forming a thin-film transistor in the pixel region, wherein the thin-film transistor comprises a gate layer and a source/drain layer formed laminatedly on the substrate, and at least one of the gate layer and the source/drain layer is formed of a single metal layer; and forming a flat layer and a reflective metal layer, which cover at least the pixel electrode region and the thin-film transistor, in sequence on the substrate, wherein the reflective metal layer is configured to be electrically connected to a drain of the thin-film transistor.

13 . The method of claim 12 , wherein the gate layer and the source/drain layer both are formed of a single metal layer.

14 . The method of claim 13 , wherein the gate layer and the source/drain layer are formed of one and the same metal.

15 . The method of claim 14 , wherein the gate layer and the source/drain layer have the same thickness.

16 . The method of claim 14 , wherein the metal comprises one of molybdenum, copper and aluminum.

17 . The method of claim 15 , wherein the gate layer and the source/drain layer both are formed of a molybdenum layer with a thickness of 2200 Å.

18 . The method of claim 12 , wherein a portion of the reflective metal layer covering the pixel electrode region is substantially flat, and the reflective metal layer is formed of one of Al, Ag and AlNd.

19 . The method of claim 18 , wherein the reflective metal layer is formed of one of Al, Ag and AlNd.

20 . The method of claim 12 , wherein the flat layer comprises a resin layer.

21 . The method of claim 12 , wherein the substrate further comprises a surrounding lead wire region, wherein the reflective metal layer is further formed on the surrounding lead wire region; the method further comprises:
forming an indium tin oxide layer, which covers a portion of the reflective metal layer located on the surrounding lead wire region, on the substrate.

22 . A totally reflective type liquid crystal display, comprising an array substrate of claim 9 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• Lv Zhijun
• Li Tailiang
• Gao Tao
• Ning ce
• Sun Shuang

Classifications

• G02F1/1362

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• G02F1/133553 Primary

  Reflecting elements (associated to illuminating devices G02F1/133605) · CPC title

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title