Semiconductor Device and Method for Manufacturing the Same

Patent metadata

Field	Value
Publication number	US-2016355398-A1
Application number	US-201514731433-A
Country	US
Kind code	A1
Filing date	Jun 5, 2015
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate comprising a MEMS region and a connection region thereon; a dielectric layer disposed on said substrate in said connection region; a poly-silicon layer disposed on said dielectric layer, wherein said poly-silicon layer serves as an etch-stop layer; a connection pad disposed on said poly-silicon layer; and a passivation layer covering said dielectric layer, wherein the passivation layer comprises an opening that exposes said connection pad and a transition region between said connection pad and said passivation layer.

2 . The semiconductor device of claim 1 , further comprising a conductive layer covering said connection pad and said poly-silicon layer in said transition region.

3 . The semiconductor device of claim 2 , wherein said conductive layer comprises a single layer comprising metal, conductive oxide, conductive nitride or combination thereof.

4 . The semiconductor device of claim 2 , wherein said conductive layer comprises multiple layers comprising metal, conductive oxide, conductive nitride or combination thereof.

5 . The semiconductor device of claim 1 , wherein said MEMS region comprises a plurality of holes and at least one MEMS diaphragm carried by said substrate.

6 . A method for manufacturing a semiconductor device, comprising:
providing a substrate comprising a MEMS region and a connection region thereon; providing a dielectric layer disposed on said substrate in said connection region; providing a poly-silicon layer disposed on said dielectric layer, wherein said poly-silicon layer serves as an etch-stop layer; providing a connection pad disposed on said poly-silicon layer; and providing a passivation layer covering said dielectric layer, wherein the passivation layer comprises an opening that exposes said connection pad and a transition region between said connection pad and said passivation layer.

7 . The method of claim 6 , further comprising a step of providing a conductive layer covering said connection pad and said poly-silicon layer in said transition region.

8 . The method of claim 7 , wherein said conductive layer comprises a single layer comprising metal, conductive oxide, conductive nitride or combination thereof.

9 . The method of claim 7 , wherein said conductive layer comprises multiple layers comprising metal, conductive oxide, conductive nitride or combination thereof.

10 . The method of claim 6 , wherein said MEMS region comprises a plurality of sealed micromachined mesh membranes carried by said substrate.

Assignees

• United Microelectronics Corp

Inventors

• Chen Yan-Da
• Chen Weng Yi
• Hsu Chang-Sheng
• Wang Kuan-Yu
• Lin Yuan Sheng

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10P14/60 Primary

  of insulating materials · CPC title

• B81C2201/014

  by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal · CPC title

• B81C1/00801

  Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer (B81C1/00595, B81C1/00468 take precedence) · CPC title