Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method

Patent metadata

Field	Value
Publication number	US-2016352364-A1
Application number	US-201615234122-A
Country	US
Kind code	A1
Filing date	Aug 11, 2016
Priority date	Oct 1, 2009
Publication date	Dec 1, 2016
Grant date	—

Abstract

A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

First claim

1 . A Viterbi detector comprising:
a soft output Viterbi algorithm (SOVA) detector adapted to receive a sequence of soft information values, the SOVA detector configured to determine a best path and an alternate path for each of these soft information values and further determine, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value, the SOVA detector further configured to utilize this third path when updating the reliability of the best path, where the SOVA detector includes first reliability metric units for the first N stages of the SOVA, detector, where N is the memory depth of a given path, and includes second reliability metric units different that the first reliability metric units for the remaining stages of the SOVA detector.

2 - 16 . (canceled)

17 . A Viterbi detector comprising:
an input terminal configured to receive a signal that represents a code word; a register; and a circuit coupled to the input terminal and to the register, the circuit configured to,
calculate path lengths according to a first set of state-transition branches,
update the path lengths more than once according to a second set of state-transition branches that is different than the first set of state-transition branches,
update the path lengths according to a third set of state-transition branches that is different than the first and second sets of state-transition branches,
recover the code word from the updated path lengths, and
load the recovered code word into the register.

18 . The Viterbi detector of claim 17 wherein the code word, comprises a set of data bits, a set of code bits, and a parity bit.

19 . The Viterbi detector of claim 17 further comprising:
a synchronization terminal configured to receive a synchronization signal; and
wherein the circuit is configured to identify the beginning of the code word in response to the synchronization signal.

20 . (canceled)

21 . A method comprising:
receiving a signal that represents a code word at an input terminal of a Viterbi detector; and operating a circuit of the Viterbi detector to
calculate path lengths according to a first set of state-transition branches,
update the path lengths more than once according to a second set of state-transition branches that is different than the first set of state-transition branches,
update the path lengths according to a third set of state-transition branches that is different than the first and second sets of state-transition branches,
recover the code word from the updated path lengths, and
load the recovered code word, into a register of the Viterbi detector.

22 . The method detector of claim 21 wherein the code word comprises a set of data bits, a set of code bits, and a parity bit.

23 . The method of claim 21 further comprising:
receiving a synchronization signal at a synchronization terminal of the Viterbi detector; and
operating the circuit to identify the beginning of the code word in response to the synchronization signal.

24 . A disk-drive system comprising:
a data-storage disk having a surface configured to store information values; a motor configured to rotate the data-storage disk; a read head configured to generate a read signal; a read-head positioning assembly configured to move the read head over the surface of the data-storage disk; and a Viterbi detector comprising a register and a circuit coupled to the read-head and the register, the circuit configured to
calculate path lengths according to a first set of state-transition branches,
update the path lengths more than once according to a second set of state-transition branches that is different than the first set of state-transition branches,
update the path lengths according to a third set of state-transition branches that is different than the first and second sets of state-transition branches,
recover the code word from the updated path lengths, and
load the recovered code word into the register.

25 . The disk-drive system of claim 24 wherein the code word comprises a set of data bits, a set of code bits, and a parity bit.

26 . The disk-drive system, of claim 24 wherein the Viterbi detector further comprises a synchronization terminal configured to receive a synchronization signal; and wherein the circuit is configured to identify the beginning of the code word in response to the synchronisation signal.

Assignees

• St Microelectronics Inc

Inventors

• Parthasarathy Sivagnanam
• Huang Lun Bin
• Risso Alessandro

Classifications

• H03M13/6343

  Error control coding in combination with techniques for partial response channels, e.g. recording · CPC title

• H03M13/4146 Primary

  soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding · CPC title

• H03M13/6502

  Reduction of hardware complexity or efficient processing · CPC title

• H03M13/3905

  Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding · CPC title

• H04L1/0055

  MAP-decoding · CPC title