Distributed Mach-Zehnder Modulator (MZM) Driver Delay Compensation

Patent metadata

Field	Value
Publication number	US-2016352325-A1
Application number	US-201514723839-A
Country	US
Kind code	A1
Filing date	May 28, 2015
Priority date	May 28, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.

First claim

1 . An electronic driver circuit for a modulator, comprising:
a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter having a first gate width, wherein the first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal; and a second delay buffer following the first delay buffer, wherein the second delay buffer is implemented as a second CMOS inverter having a second gate width smaller than the first gate width of the first CMOS inverter, and wherein the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.

2 . The electronic driver circuit of claim 1 , further comprising a third delay buffer following the second delay buffer, the third delay buffer implemented as a third CMOS inverter having a third gate width smaller than the second gate width of the second CMOS inverter, wherein the third CMOS inverter produces a third delayed electrical signal from the second delayed electrical signal produced by the second CMOS inverter.

3 . The electronic driver circuit of claim 2 , wherein the first delayed electrical signal is provided to a first output buffer, the second delayed electrical signal is provided to a second output buffer, and the third delayed electrical signal is provided to a third output buffer.

4 . The electronic driver circuit of claim 3 , wherein each of the first output buffer, the second output buffer, and the third output buffer is implemented as an output CMOS inverter.

5 . The electronic driver circuit of claim 2 , wherein the second delay buffer includes a first metal trace operably coupled to the second CMOS inverter and the third delay buffer includes a second metal trace operably coupled to the second CMOS inverter.

6 . The electronic driver circuit of claim 5 , wherein the first CMOS inverter, the second CMOS inverter, and the third CMOS inverter each produce an active delay, and wherein the first metal trace and the second metal trace each produce a passive delay.

7 . The electronic driver circuit of claim 6 , wherein the active delay is 4 picoseconds (ps) and the passive delay is 4 ps.

8 . The electronic driver circuit of claim 2 , wherein the first gate width is 4 w, the second gate width is 2 w, and the third gate width is w, where w is a unit gate width, such that the gate width of each of the successive buffer stages is reduced by a factor of 2.

9 . The electronic driver circuit of claim 2 , wherein the first gate width is 16 w, the second gate width is 4 w, and the third gate width is w, where w is a unit gate width, such that the gate width of each of the successive buffer stages is reduced by a factor of 4.

10 . An electronic driver circuit for a modulator, comprising:
a first delay stage including a first active delay element having a first gate width, wherein the first active delay element introduces a first active delay to a received electrical signal to produce a first delayed signal; and a second delay stage operably coupled to the first delay stage, wherein the second delay stage includes a first passive delay element and a second active delay element, wherein the second active delay element has a second gate width smaller than the first gate width of the first active delay element, and wherein the first passive delay element introduces a first passive delay and the second active delay element introduces a second active delay to the first delayed signal to produce a second delayed signal.

11 . The electronic driver circuit of claim 10 , wherein a third delay stage is operably coupled to the second delay stage, wherein the third delay stage includes a second passive delay element and a third active delay element, wherein the third active delay element has a third gate width smaller than the second gate width, and wherein the second passive delay element introduces a second passive delay and the third active delay element introduces a third active delay to the second delayed signal to produce a third delayed signal.

12 . The electronic driver circuit of claim 11 , wherein each of the first active delay element, the second active delay element, and the third active delay elements is a complementary metal-oxide-semiconductor (CMOS) inverter disposed in a delay buffer.

13 . The electronic driver circuit of claim 11 , wherein the first delayed signal is provided to a first output buffer, the second delayed signal is provided to a second output buffer, and the third delayed signal is provided to a third output buffer.

14 . The electronic driver circuit of claim 13 , wherein each of the first output buffer, the second output buffer, and the third output buffer is a complementary metal-oxide-semiconductor (CMOS) inverter.

15 . The electronic driver circuit of claim 10 , wherein the passive delay element is a metal trace.

16 . The electronic driver circuit of claim 15 , wherein the metal trace has a length of at least 650 micrometers (μm).

17 . A method of driving a modulator, comprising:
generating, at first delay stage, a first delayed electrical signal from a received electrical signal using a first complementary metal-oxide-semiconductor (CMOS) inverter having a first gate width; outputting the first delayed electrical signal to a first output buffer and a second delay stage; generating, at the second delay stage, a second delayed electrical signal from the first delayed electrical signal using a passive delay element and a second CMOS inverter, the second CMOS inverter having a second gate width smaller than the first gate width of the first CMOS inverter; and outputting the second delayed electrical signal to a second output buffer.

18 . The method of claim 17 , further comprising outputting the second delayed electrical signal to a third delay stage and generating, at the third delay stage, a third delayed electrical signal from the second delayed electrical signal using another passive delay element and a third CMOS inverter, the third CMOS inverter having a third gate width smaller than the second gate width of the second CMOS inverter.

19 . The method of claim 18 , further comprising outputting the third electrical signal to a third output buffer.

20 . The method of claim 19 , wherein the first output buffer, the second output buffer, and the third output buffer are each implemented as an output CMOS inverter, and wherein each of the passive delay elements is a metal trace.

Assignees

• Futurewei Technologies Inc

Inventors

• Chen Morgan
• Gu Yifan
• Lee Hungyi
• Gu Liang
• Dang Yen
• Lei Gong
• Cao Yuming
• Shen Xiao
• Bai Yu Sheng

Classifications

• G02F1/2255 Primary

  controlled by a high-frequency electromagnetic component in an electric waveguide structure · CPC title

• G02F2001/212

  Physics · mapped topic

• H03K17/284 Primary

  in field effect transistor switches · CPC title

• G02F1/212

  Mach-Zehnder type · CPC title

• H03K5/134

  with field-effect transistors · CPC title