Regulator with high speed nonlinear compensation

Patent metadata

Field	Value
Publication number	US-2016352128-A1
Application number	US-201615062348-A
Country	US
Kind code	A1
Filing date	Mar 7, 2016
Priority date	Jun 1, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

An apparatus including a proportional gain circuit, an integral gain circuit, a limit circuit, a gain booster circuit and a combiner. The gain circuits apply a proportional gain and an integral gain to an error signal, and the combiner combines both gained error signals to provide a control signal. The limit circuit applies a limit function that limits the proportional gain to a magnitude. The gain booster circuit increases gain while the limit function is being applied. The increased gain may be applied to only the integral gain, or to both the integral and proportional gains such as by boosting gain of the error signal. The apparatus may be a regulator that may include multiple control loops providing multiple error signals, in which a mode selector selects one of the error signals to control regulation. The limit function increases stability while the boosted gain improves transient response during mode transitions.

First claim

1 . An apparatus, comprising:
a proportional gain circuit that applies a proportional gain to an error signal to provide a proportional gain signal; an integral gain circuit that applies an integral gain to said error signal to provide an integral gain signal; a limit circuit that provides a limited proportional gain signal that follows said proportional gain signal up to a magnitude and that applies a limit function to limit said limited proportional gain signal to said magnitude while a magnitude of said proportional gain signal is greater than said magnitude; a gain booster circuit that increases gain of at least said integral gain signal while said limit function is applied; and a combiner that combines said limited proportional gain signal with said integral gain signal to provide a control signal on a control node that controls operation of the regulator.

2 . The apparatus of claim 1 , wherein:
said limit circuit comprises an adder that subtracts said limited proportional gain signal from said proportional gain signal to provide a proportional limit signal indicative thereof; wherein said integral gain circuit comprises a first integral gain circuit that applies a first integral gain to said error signal to provide a first integral gain signal; wherein said gain booster circuit comprises a second integral gain circuit that applies a second integral gain to said proportional limit signal to provide a second integral gain signal; and further comprising a summing circuit that combines said first and second integral gain signals to provide said integral gain signal.

3 . The apparatus of claim 1 , wherein said gain booster circuit increases a gain of said error signal while said limit function is applied.

4 . The apparatus of claim 1 , wherein:
said limit circuit asserts a limit signal indicating whether said limit function is active; and wherein said gain booster circuit comprises:
a first gain circuit that applies a first gain to said error signal to provide a first amplified error signal;
a second gain circuit that applies a second gain to said error signal to provide a second amplified error signal; and
a select circuit that selects between said first and second amplified error signals based on said limit signal.

5 . The apparatus of claim 1 , wherein:
said proportional gain circuit, said integral gain circuit and said combiner comprises:
a resistor circuit coupled between a summing node and an integral node;
a capacitor circuit coupled between said integral node and a reference node;
a first transconductance amplifier having an input receiving said error signal and an output that provides a current signal indicative thereof to said summing node;
a first buffer amplifier having an input coupled to said integral node and having an output providing said integral gain signal to a buffered integral node;
a second buffer amplifier having an input coupled to said summing node and having an output providing said proportional gain signal to a buffered summing node; and
a resistive device coupled between said buffered summing node and said control node; and
wherein said limit circuit comprises a clamp circuit coupled between said buffered integral node and said control node.

6 . The apparatus of claim 5 , wherein said clamp circuit prevents a voltage of said control node from rising above a voltage of said buffered integral node by an upper limit amount.

7 . The apparatus of claim 5 , wherein said clamp circuit comprises:
a first clamp circuit that prevents a voltage of said control node from rising above a voltage of said buffered integral node by an upper limit amount; and a second clamp circuit that prevents a voltage of said control node from falling below a voltage of said buffered integral node by a lower limit amount.

8 . The apparatus of claim 7 , wherein said first and second clamp circuits each comprise a diode and a voltage source.

9 . The apparatus of claim 5 , wherein said gain booster circuit comprises a second transconductance amplifier having a first input coupled to said summing node, having a second input coupled to said control node and having an output coupled to said integral node.

10 . The apparatus of claim 5 , wherein:
said limit circuit further comprises a limit detector having inputs coupled to said buffered summing node and said control node and having an output that asserts a limit signal indicating whether said limit function is active; and wherein said first transconductance amplifier has a gain adjust input receiving said limit signal, wherein said first transconductance amplifier increases gain applied to said error signal when said limit signal indicates that said limit function is active.

11 . The apparatus of claim 5 , further comprising select logic that selects from among a plurality of loop error signals to provide said error signal to said first transconductance amplifier.

12 . The apparatus of claim 11 , further comprising a loop selector that monitors said plurality of loop error signals including an input voltage error, an output voltage error, an input current error and a battery current error, and that controls said select logic.

13 . The apparatus of claim 12 , further comprising wherein said proportional gain circuit, said integral gain circuit, said limit circuit, said gain booster circuit, and said combiner form a compensation circuit provided within a current mode controller of a regulator, wherein said current mode controller receives said error signal and an inductor current signal and develops a pulse width modulation signal for controlling said regulator and that develops a battery control signal for controlling a battery current.

14 . An electronic device, comprising:
a system load; an input node for receiving an adapter voltage and for developing an input voltage; a battery node for receiving a battery voltage; a regulator coupled to said input node and said battery node and that provides an output voltage to said system load, said regulator comprising:
a converter that converts said input voltage to said output voltage based on a pulse control signal;
a loop selector that monitors a plurality of loop error signals including an input voltage error, an output voltage error, an input current error and a battery current error, and that selects one of said plurality of loop error signals to provide a selected error signal;
a current mode controller that monitors said selected error signal and a current through said converter and that develops said pulse control signal, wherein said current mode controller comprises:
a proportional gain circuit that applies a proportional gain to said selected error signal to provide a proportional gain signal;
an integral gain circuit that applies an integral gain to said selected error signal to develop an integral gain signal;
a limit circuit that provides a limited proportional gain signal that follows said proportional gain signal up to a magnitude and that applies a limit function to limit said limited proportional gain signal to said magnitude while a magnitude of said proportional gain signal is greater than said magnitude;
a gain booster circuit that increases gain of at least said integral gain signal while said limit function is applied; and
a combiner that combines said limited proportional gain signal with said integral gain signal to provide a control signal on a control node used to develop said pulse control signal.

15 . The electronic device of claim 14 , wherein:
said integral gain circuit comprises a first amplifier that applies a current error signa

Assignees

• Intersil Americas LLC

Inventors

• Houston M Jason
• Solie Eric M
• Shah Mehul D

Classifications

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02J7/02

  for charging batteries from AC mains by converters · CPC title

• H02J7/865 Primary

  Battery or charger load switching, e.g. concurrent charging and load supply (H02J7/50 takes precedence) · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• H03K5/08

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title