Manufacturing method of solar cell
US-2015056743-A1 · Feb 26, 2015 · US
Dry etch method for texturing silicon and device
US2016351733A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016351733-A1 |
| Application number | US-201514727450-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 1, 2015 |
| Priority date | Jun 1, 2015 |
| Publication date | Dec 1, 2016 |
| Grant date | — |
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Abstract
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A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.
First claim
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1 .- 14 . (canceled) 15 . A photovoltaic device, comprising: a textured silicon substrate including pyramidal shaped recesses formed in a surface thereof, the pyramidal shaped recesses including exposed (111) silicon surfaces; a junction layer formed in accordance with the textured silicon substrate; a first electrode layer formed in contact with the silicon substrate; and a second electrode layer formed over the junction layer. 16 . The device as recited in claim 15 , wherein the pyramidal shaped recesses are formed by exposing the silicon wafer to cracked sulfur species to etch the wafer to expose the (111) silicon surfaces. 17 . The device as recited in claim 15 , wherein the pyramidal shaped recesses are randomly located across the surface. 18 . The device as recited in claim 15 , wherein the pyramidal shaped recesses formed in the wafer have a depth of between about 10 nm and about 300 nm. 19 . The device as recited in claim 15 , wherein the pyramidal shaped recesses formed in the wafer have a size of between about 20 nm and about 100 nm. 20 . The device as recited in claim 15 , wherein the junction layer include one of a p-i-n stack, n-i-p stack, a p-n junction or n-p junction.
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H01L31/02363Primary
Electricity · mapped topic
the films including only Group IV materials · CPC title
of the semiconductor bodies, e.g. textured active layers · CPC title
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Frequently asked questions
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- What does patent US2016351733A1 cover?
- A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H01L31/02363. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).