Method of forming metal contacts in the barrier layer of a group iii-n hemt

Patent metadata

Field	Value
Publication number	US-2016351685-A1
Application number	US-201615237041-A
Country	US
Kind code	A1
Filing date	Aug 15, 2016
Priority date	Apr 3, 2013
Publication date	Dec 1, 2016
Grant date	—

Abstract

Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

First claim

What is claimed is:

1 : A method of forming a high electron mobility transistor comprising:
forming a layered structure including a barrier layer directly on a channel layer directly on a buffer layer directly on a substrate; forming metal contact openings in the layered structure by etching with a first gas combination, each of the metal contact openings having a first bottom surface that lies above and spaced apart from the channel layer; and etching the layered structure with a second gas combination to deepen each metal contact opening a distance to a second bottom surface, the second bottom surface lying above and spaced apart from the channel layer, wherein the second gas combination etches more of the barrier layer than does the first gas combination and wherein the first gas combination also etches through a cap layer on the barrier layer, and through a passivation layer on the cap layer, the cap layer including GaN, the passivation layer including silicon nitride.

2 : The method of claim 1 , wherein the first gas combination includes boron trichloride (BCl3) and sulfur hexafluoride (SF6), and the second gas combination includes boron trichloride (BCl 3 ) and chlorine (Cl 2 ).

3 : The method of claim 1 , further comprising depositing a metal contact layer that contacts each second bottom surface and fills the metal contact openings.

4 : The method of claim 3 and further comprising planarizing the metal contact layer to form a number of spaced-apart metal contacts that lie in the metal contact openings.

5 : The method of claim 1 , wherein the channel layer comprises GaN.

6 : The method of claim 1 , wherein the barrier layer is AlGaN.

7 : A method of forming a high electron mobility transistor comprising:
forming a channel layer over a substrate; forming a barrier layer over the channel layer, the barrier layer including a GaN material; etching the GaN material of the barrier layer with a gas combination that includes boron trichloride (BCl 3 ) and sulfur hexafluoride (SF 6 ) to form a number of metal contact openings, each of the metal contact openings having a bottom surface that lies above and spaced apart from a top surface of the channel layer; and etching the GaN material of the barrier layer exposed by the metal contact openings with a gas combination that includes boron trichloride (BCl 3 ) and chlorine (Cl 2 ) to deepen each metal contact opening to a second bottom surface, the second bottom surface lying above and spaced apart from the top surface of the channel layer.

8 : The method of claim 7 , further comprising depositing a metal contact layer that contacts each second bottom surface and fills the metal contact openings.

9 : The method of claim 8 , further comprising planarizing the metal contact layer to form a number of spaced-apart metal contacts that lie in the number of metal contact openings.

10 : The method of claim 7 , wherein the gas combination that includes BCl 3 and SF 6 also etches through a cap layer over the barrier layer, and through a passivation layer over the cap layer.

11 : The method of claim 10 , wherein the cap layer includes GaN and the passivation layer includes silicon nitride.

12 : The method of claim 7 , wherein the gas combination that includes BCl 3 and SF 6 also etches through a passivation layer over the barrier layer.

13 : The method of claim 12 , wherein the passivation layer includes silicon nitride.

14 : The method of claim 7 , wherein the channel layer includes GaN.

15 : The method of claim 7 , wherein the GaN material of the barrier layer is AlGaN.

16 : A method of forming a high electron mobility transistor comprising:
forming a buffer layer over a substrate; forming a channel layer over the buffer layer; forming an AlGaN layer over the channel layer; forming a cap layer over the AlGaN layer; forming a layer of SiN over the cap layer; forming a source contact and a drain contact through the layer of SiN, the cap layer, and into the layer of AlGaN, wherein a bottom surface of the source contact and a bottom surface of the drain contact are within the AlGaN layer and are spaced apart from the channel layer.

17 : The method of claim 16 , wherein the channel layer comprises GaN.

18 : The method of claim 16 , wherein the cap layer comprises GaN.

19 : The method of claim 16 , wherein forming the source contact and the drain contact comprises:
etching the layer of SiN, cap layer, and AlGaN layer with a gas combination that includes boron trichloride (BCl 3 ) and sulfur hexafluoride (SF 6 ) to form a source contact opening and a drain contact opening; etching the AlGaN layer with a second gas combination that includes boron trichloride (BCl 3 ) and chlorine (Cl 2 ) to deepen the source contact opening and the drain contact opening; depositing a metal contact layer in the source contact opening and the drain contact opening; and planarizing the metal contact layer to form the source contact and the drain contact.

20 : The method of claim 19 , wherein the metal contact layer comprises a titanium layer, an aluminum copper layer over the titanium layer, and a titanium nitride layer over the aluminum copper layer.

Assignees

• Texas Instruments Inc

Inventors

• Kondo Yoshikazu
• Wada Shoji
• Yamasaki Hiroshi
• Iwamoto Masahiro

Classifications

• H10P50/246

  of Group III-V materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title