Method for manufacturing insulated gate type switching device, and insulated gate type switching device

Patent metadata

Field	Value
Publication number	US-2016351680-A1
Application number	US-201415114461-A
Country	US
Kind code	A1
Filing date	Oct 6, 2014
Priority date	Feb 17, 2014
Publication date	Dec 1, 2016
Grant date	—

Abstract

A method is provided for manufacturing an insulated gate type switching device. The method includes: implanting second conductivity type impurities into a surface of a semiconductor substrate so as to form a second region of a second conductivity type in the surface; forming a third region of the second conductivity type having a second conductivity type impurity density lower than the second region on the surface by epitaxial growth: and forming a trench gate electrode.

First claim

1 . A method of manufacturing an insulated gate type switching device, the method comprising:
implanting second conductivity type impurities into a surface of a semiconductor substrate including a first region of a first conductivity type so as to form a second region of a second conductivity type in a range in the semiconductor substrate that is exposed on the surface; forming a third region of the second conductivity type on the surface by epitaxial growth after the formation of the second region, the third region having a second conductivity type impurity density lower than a second conductivity type impurity density in the second region; forming a fourth region of the first conductivity type being in contact with the third region and separated from the first region by the second and third regions; and forming a trench gate electrode facing the second and third regions via an insulating film.

2 . The method of claim 1 , wherein a first conductivity type impurity density in the third region is lower than the first conductivity type impurity density in the first region.

3 . An insulated gate type switching device comprising:
a first region of a first conductivity type; a second region of a second conductivity type provided on the first region; a third region of the second conductivity type provided on the second region and having a second conductivity type impurity density lower than a second conductivity type impurity density in the second region; a fourth region of the first conductivity type being in contact with the third region and separated from the first region by the second and the third regions; and a trench gate electrode facing the second and the third regions via an insulating film, wherein first conductivity type impurity densities in the first and second regions are substantially constant, a second conductivity type impurity density distribution in a thickness direction of the second region has a local maximal value, and a second conductivity type impurity density in the third region is substantially constant.

4 . The insulated gate type switching device of claim 3 , wherein a first conductivity type impurity density in the third region is lower than the first conductivity type impurity density in the first region.

Assignees

• Soeno Akitaka
• Takeuchi Yuichi
• Soejima Narumasa
• Toyota Motor Co Ltd
• Denso Corp

Inventors

• Soeno Akitaka
• Takeuchi Yuichi
• Soejima Narumasa

Classifications

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D62/8325 Primary

  Silicon carbide · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title