Semiconductor Device and Method of Balancing Surfaces of an Embedded PCB Unit with a Dummy Copper Pattern

Patent metadata

Field	Value
Publication number	US-2016351419-A1
Application number	US-201615235008-A
Country	US
Kind code	A1
Filing date	Aug 11, 2016
Priority date	Oct 29, 2013
Publication date	Dec 1, 2016
Grant date	—

Abstract

A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

First claim

What is claimed:

1 . A method of making a semiconductor device, comprising:
providing a substrate; forming a plurality of first contact pads over a first surface of the substrate; forming a plurality of second contact pads over a second surface of the substrate; and forming a dummy pattern over the second surface of the substrate.

2 . The method of claim 1 , further including forming an indentation in a sidewall of the substrate.

3 . The method of claim 1 , further including forming an opening through the substrate.

4 . The method of claim 1 , wherein an area of the first surface covered by the first contact pads is approximately equal to an area of the second surface covered by the second contact pads plus an area of the second surface covered by the dummy pattern.

5 . The method of claim 1 , further including:
forming an insulating layer over the second surface of the substrate; and forming a dummy opening in the insulating layer.

6 . The method of claim 1 , further including:
disposing a semiconductor die adjacent to the substrate; and depositing an encapsulant over the semiconductor die and substrate.

7 . A method of making a semiconductor device, comprising:
providing a substrate; forming a first conductive layer over a first surface of the substrate; forming a second conductive layer over a second surface of the substrate; and forming a dummy pattern over the second surface of the substrate to balance the first conductive layer and second conductive layer.

8 . The method of claim 7 , further including forming an indentation in a sidewall of the substrate.

9 . The method of claim 7 , further including forming an opening through the substrate.

10 . The method of claim 9 , further including depositing an encapsulant in the opening of the substrate.

11 . The method of claim 7 , further including:
forming an insulating layer over the second surface of the substrate; and forming a dummy opening in the insulating layer.

12 . The method of claim 7 , wherein the first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

13 . The method of claim 7 , further including:
disposing a semiconductor die adjacent to the substrate; and depositing an encapsulant over the semiconductor die and substrate.

14 . A method of making a semiconductor device, comprising:
providing a substrate; forming a first conductive layer over a first surface of the substrate; and forming a dummy pattern over a second surface of the substrate.

15 . The method of claim 14 , further including forming an indentation in a sidewall of the substrate.

16 . The method of claim 14 , further including forming an opening through the substrate.

17 . The method of claim 16 , further including depositing an encapsulant in the opening of the substrate.

18 . The method of claim 14 , further including:
forming an insulating layer over the second surface of the substrate; and forming a dummy opening in the insulating layer.

19 . The method of claim 14 , wherein the first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

20 . A semiconductor device, comprising:
a substrate; a first conductive layer formed over a first surface of the substrate; and a dummy pattern formed over a second surface of the substrate.

21 . The semiconductor device of claim 20 , wherein a sidewall of the substrate includes an indentation.

22 . The semiconductor device of claim 20 , wherein the substrate includes an opening.

23 . The semiconductor device of claim 22 , further including an encapsulant disposed in the opening of the substrate.

24 . The semiconductor device of claim 20 , wherein the first surface of the substrate includes a width greater than a width of the second surface of the substrate.

25 . The semiconductor device of claim 20 , further including:
a semiconductor die disposed adjacent to the substrate; and an encapsulant deposited over the semiconductor die and substrate.

Assignees

• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Chen Kang
• Goh Hin Hwa
• Shim Il Kwon

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title