Organic Light Emitting Display and Circuit Thereof

Patent metadata

Field	Value
Publication number	US-2016351122-A1
Application number	US-201615164554-A
Country	US
Kind code	A1
Filing date	May 25, 2016
Priority date	May 28, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

An organic light emitting display comprises a display panel having a plurality of pixels, a gate drive circuit that drives scan lines and emission lines on the display panel, and a data drive circuit that drives data lines on the display panel. Each of the pixels is arranged in an nth row. A single frame for the organic light emitting display comprises an initial period in which the gate voltage of a driving transistor is initialized, a sampling period for compensating the threshold voltage of the driving transistor, and a light emission period in which an organic light emitting diode emits light. A value corresponding to an image signal to be displayed by the organic light emitting diode is applied to a data line during the sampling period, and an initial voltage is applied to one electrode of a capacitor during the initial period.

First claim

What is claimed is:

1 . An organic light emitting display comprising:
a display panel having a plurality of pixels; a gate drive circuit that drives scan lines and emission lines on the display panel; and a data drive circuit that drives data lines on the display panel, each of the pixels arranged in an nth row (n is a natural number) comprising: a driving transistor having a gate electrode connected to a node A, a source electrode connected to a node B, and a drain electrode connected to a node C, and the driving transistor controlling a driving current applied to an organic light emitting diode; a first transistor that is connected between the data lines and the node B; a second transistor that is connected between the node A and a high-level driving voltage input terminal; a third transistor that is connected to the node B and the organic light emitting diode; a fourth transistor that is connected to the node C and the high-level driving voltage input terminal; a fifth transistor that is connected to the node A and the node C; a sixth transistor that is connected between a node D and an initial voltage input terminal, the node D located between the third transistor and the organic light emitting diode; and a capacitor that is connected to the node A and the node D.

2 . The organic light emitting display of claim 1 , wherein a (j−1)th scan signal in which a data voltage is provided to the pixels arranged in a (j−1)th row has a turn-on voltage during a (j−1)th horizontal period, a jth scan signal has the turn-on voltage in which the data voltage is provided to the pixels arranged in a jth row during a jth horizontal period, and an emission signal provided to the jth row has the turn-on voltage after the jth scan signal is inverted to a turn-off voltage.

3 . The organic light emitting display of claim 2 , wherein, during the (j−1)th horizontal period, the second transistor applies the high-level driving voltage received from the high-level driving voltage input terminal to the node A, in response to the (j−1)th scan signal.

4 . The organic light emitting display of claim 3 , wherein, during the jth horizontal period, the first transistor applies the data voltage received from the data line to the node B, in response to the jth scan signal, and the fifth transistor connects the node A and the node C to operate the driving transistor, in response to the jth scan signal.

5 . The organic light emitting display of claim 4 , wherein, during a (j+1)th horizontal period, the fourth transistor connects the high-level driving voltage input terminal and the node C, in response to the emission signal, and the third transistor connects the node B and the node D, in response to the emission signal, and the node D corresponds to an operating voltage of the organic light emitting diode from the initial voltage level by the driving current, and a difference between the initial voltage level and the operating voltage of the organic light emitting diode is applied to the node A so as to emit light of the organic light emitting diode while compensating the threshold voltage of the driving transistor.

6 . The organic light emitting display of claim 1 , wherein a gate electrode of the sixth transistor is connected to a (j−1)th scan line, and during a (j−1)th horizontal period, the sixth transistor applies the initial voltage received from the initial voltage input terminal to the node D, in response to a (j−1)th scan signal.

7 . The organic light emitting display of claim 1 , wherein a gate electrode of the sixth transistor is connected to a jth scan line, and during a jth horizontal period, the sixth transistor applies the initial voltage received from the initial voltage input terminal to the node D, in response to a jth scan signal.

8 . The organic light emitting display of claim 7 , wherein each of the pixels arranged in the jth row further comprises a seventh transistor that is connected between the node D and the initial voltage input terminal and that is switched on in response to a (j−1)th scan signal.

9 . The organic light emitting display of claim 8 , wherein, during a (j−1)th horizontal period, the seventh transistor provides the initial voltage to the node D, in response to the (j−1)th scan signal.

10 . The organic light emitting display of claim 9 , wherein the initial voltage is lower than the driving voltage of the organic light emitting diode.

11 . The organic light emitting display of claim 2 , wherein the jth horizontal period further includes a high-voltage holding period, and a high-level driving voltage is applied to the node A in response to the (j−1)th scan signal during the high-voltage holding period.

12 . The organic light emitting display of claim 6 , wherein the jth horizontal period further includes a high-voltage holding period, and a high-level driving voltage is applied to the node A in response to the (j−1)th scan signal during the high-voltage holding period.

13 . The organic light emitting display of claim 7 , wherein the jth horizontal period further includes a high-voltage holding period, and a high-level driving voltage is applied to the node A in response to the (j−1)th scan signal during the high-voltage holding period.

14 . The organic light emitting display of claim 1 , wherein at least one among the second transistor and the fifth transistor has a double-gate structure.

15 . The organic light emitting display of claim 1 , further comprising a metal layer under a semiconductor layer of the driving transistor.

16 . The organic light emitting display of claim 1 , wherein a first electrode of the capacitor that receives an initial voltage from the initial voltage input terminal corresponds to the gate electrode of the driving transistor.

17 . The organic light emitting display of claim 1 , wherein a first electrode of the capacitor that receives an initial voltage from the initial voltage input terminal is disposed in an area corresponding to a semiconductor layer of the fifth transistor that operates during a sampling period.

18 . A circuit of an organic light emitting display, the circuit comprising:
a transistor array having at least one transistor; and a capacitor that is connected between an initial voltage input terminal and the at least one transistor, the capacitor having a first electrode and a second electrode, wherein the area of the first electrode that receives an initial voltage is larger than the area of the second electrode.

19 . The circuit of claim 18 , wherein the first electrode is disposed in an area corresponding to a semiconductor layer of a transistor that operates during a sampling period.

20 . The circuit of claim 18 , wherein the transistor array is on a flexible substrate, and comprising a driving transistor, and a metal layer under a semiconductor layer of the driving transistor.

21 . The circuit of claim 18 , wherein the first electrode of the capacitor is not connected to a high-level driving voltage input terminal, and is connected to the initial voltage input terminal, thereby reducing the number of contact holes.

22 . The circuit of claim 18 , further comprising;
an organic light emitting diode having an anode connected to the first electrode of the capacitor and a cathode opposite to the anode, wherein a driving transistor in the transistor array is compensated by the capacitor that receives the initial voltage.

23 . The circuit of claim 18 , wherein a

Assignees

• Lg Display Co Ltd

Inventors

• Jung Sanghoon
• Kim Jungchul
• Kwon Junyoung
• Suk Jungyoup
• Sung Kiyoung

Classifications

• G09G2330/028

  Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/2085

  Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination · CPC title