Frequency-domain high-speed bus signal integrity compliance model

Patent metadata

Field	Value
Publication number	US-2016350195-A1
Application number	US-201514721862-A
Country	US
Kind code	A1
Filing date	May 26, 2015
Priority date	May 26, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

Embodiments of the present disclosure provide apparatus for testing channel compliance. The apparatus generally performs operations that includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

First claim

1 - 8 . (canceled)

9 . A computer program product for testing channel compliance, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
identify at least one design criteria; and determine boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria, wherein the boundary sets are used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

10 . The computer program product of claim 9 , wherein the boundary sets are determined by using time-domain simulations of S-parameters representing one of a plurality of channel variations, wherein each channel variation is simulated in the time domain by sweeping a plurality of equalization settings.

11 . The computer program product of claim 9 , wherein the frequency domain parameters for the particular channel is derived from S-parameters indicative of a frequency response of the particular channel.

12 . The computer program product of claim 9 , wherein the design criteria comprises a desired bit error rate for a particular set of bus transmitter and receiver properties.

13 . The computer program product of claim 10 , wherein the boundary sets are determined using a genetic algorithm.

14 . The computer program product of claim 10 , wherein the signal channel is part of a communication bus and the boundary sets of frequency domain parameters comprise at least one parameter related to insertion loss and at least one parameter related to a crosstalk ratio at a fundamental frequency of the bus.

15 . The computer program product of claim 10 , wherein the particular signal channel is used for communication between a first and second components and the boundary sets are determined for at least one known property of the first and second components.

16 . The computer program product of claim 10 , wherein the verifying comprises:
determining whether the particular signal channel is compliant based on a comparison of the frequency domain parameters for the particular channel to frequency domain parameters of a first boundary set; and if not, determining whether the particular signal channel is compliant based on a comparison of the frequency domain parameters for the particular channel to frequency domain parameters of a second boundary set.

17 . A processing system, comprising:
at least one processor configured to:
identify at least one design criteria; and
determine boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria, wherein the boundary sets are used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels; and
a memory coupled to the at least one processor.

18 . The processing system of claim 17 , wherein the design criteria comprises a desired bit error rate for a particular set of bus transmitter and receiver properties.

19 . The processing system of claim 17 , wherein the boundary sets are determined using a genetic algorithm.

20 . The processing system of claim 17 , wherein the signal channel is part of a communication bus and the boundary sets of frequency domain parameters comprise at least one parameter related to insertion loss and at least one parameter related to a crosstalk ratio at a fundamental frequency of the bus.

Assignees

• IBM

Inventors

• Becker Wiren D
• Dreps Daniel M
• Hejase Jose A
• Wiedemeier Glen A
• Win Si T

Classifications

• G06F11/263

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G06F11/2221

  to test input/output devices or peripheral units · CPC title

• G06F11/273 Primary

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title

• H04L43/0823

  Errors, e.g. transmission errors · CPC title

• H04L2001/0094

  Bus · CPC title