Apparatus and method for detecting and mitigating bit-line opens in flash memory
US-2016283320-A1 · Sep 29, 2016 · US
Methods and apparatuses for error correction
US2016350184A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016350184-A1 |
| Application number | US-201514721913-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 26, 2015 |
| Priority date | May 26, 2015 |
| Publication date | Dec 1, 2016 |
| Grant date | — |
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Abstract
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Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.
First claim
Opening claim text (preview).
What is claimed is: 1 . An apparatus comprising: a memory device having a plurality of multi-level cells; an encoder circuit coupled to the memory device and configured to store a plurality of data bits in the plurality of multi-level cells; and a decoder circuit coupled to the memory device and configured to identify one or more erroneous cells in the plurality of multi-level cells, convert the erroneous cells to erasures, and correct the erasures. 2…
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- G11C29/52Primary
Physics · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- G06F11/1072Primary
Physics · mapped topic
Electricity · mapped topic
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- What does patent US2016350184A1 cover?
- Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may f…
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C29/52. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).