Bandwidth/resource management for multithreaded processors

US2016350152A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016350152-A1
Application numberUS-201514866012-A
CountryUS
Kind codeA1
Filing dateSep 25, 2015
Priority dateMay 29, 2015
Publication dateDec 1, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of managing shared resources in a multithreaded processor comprising two or more processing threads, the method comprising: determining danger levels for the two or more threads, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource; detecting priority levels associated with the two or more threads, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable; and scheduling the two or more threads based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads. 2 . The method of claim 1 , further comprising, throttling at least one low priority thread whose failure to meet a deadline is acceptable, wherein throttling the low priority thread comprises preventing or delaying scheduling of a low priority transaction from the low priority thread, wherein the low priority transaction will consume shared resources if scheduled. 3 . The method of claim 2 , further comprising, scheduling a high priority transaction from at least one high priority thread whose failure to meet a deadline is unacceptable, wherein shared resources for the high priority thread are made available based on throttling the low priority transaction. 4 . The method of claim 1 , wherein determining the danger levels for the two or more threads is based on an internal danger level of the two or more threads and an external danger level of one or more cores of a system comprising the multithreaded processor. 5 . The method of claim 4 , wherein the internal danger level is based on one or more of a danger level provided by a software programmable register programmed with danger levels for each thread, a danger level provided by a timer if the timer expires before a task associated with a thread is completed, a danger level provided by a bandwidth monitor for each thread, or a danger level provided by a latency monitor for each thread. 6 . The method of claim 5 , further comprising providing the internal danger level to a Quality of Service (QoS) controller for managing QoS policies of the one or more cores of the system. 7 . The method of claim 4 , wherein the external danger level is based on a Quality of Service (QoS) of the one or more cores of the system. 8 . The method of claim 1 , comprising grouping transactions from the one or more threads in a scoreboard, based on priority levels associated with the two or more threads. 9 . The method of claim 1 , wherein the multithreaded processor is one of a digital signal processor (DSP), general purpose processor (GPP), or a central processing unit (CPU). 10 . The method of claim 1 , comprising scheduling one or more low priority transactions if the determined danger levels for the two or more threads is low, and scheduling one or more high priority transactions while delaying scheduling of one or more low priority transactions if the determined danger levels of the two or more threads is high. 11 . A processing system comprising: a multithreaded processor configured to process two or more processing threads; a danger aggregator configured to determine danger levels for the two or more threads, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource; a transaction scoreboard configured to track priority levels associated with the two or more threads, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable; and a dequeue engine configured to schedule the two or more threads based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads. 12 . The processing system of claim 11 , further comprising, a scheduler configured to throttle at least one low priority thread whose failure to meet a deadline is acceptable. 13 . The processing system of claim 12 , wherein the scheduler is further configured to schedule a high priority transaction from at least one high priority thread whose failure to meet a deadline is unacceptable, wherein resources are shared between the throttled low priority thread and the high priority thread. 14 . The processing system of claim 13 , wherein the resources comprise one or more of an interconnect or a memory. 15 . The processing system of claim 11 , wherein the danger aggregator is configured to determine the danger levels for the two or more threads based on an internal danger level of the two or more threads and an external danger level of one or more cores of the processing system. 16 . The processing system of claim 15 , wherein the internal danger level is based on one or more of a danger level provided by a software programmable register programmed with danger levels for each thread, a danger level provided by a timer if the timer expires before a task associated with a thread is completed, a danger level provided by a bandwidth monitor for each thread, or a danger level provided by a latency monitor for each thread. 17 . The processing system of claim 16 , wherein the danger aggregator is further configured to provide the internal danger level to a Quality of Service (QoS) controller configured to manage QoS policies of the one or more cores of the processing system. 18 . The processing system of claim 15 , wherein the external danger level is based on a Quality of Service (QoS) of the one or more cores and the multithreaded processor. 19 . The processing system of claim 11 , wherein the transaction scoreboard is configured to group transactions from the one or more threads, based on priority levels associated with the two or more threads. 20 . The processing system of claim 11 , wherein the dequeue engine is configured to schedule one or more low priority transactions if the determined danger levels for the two or more threads is low, and schedule one or more high priority transactions and delay one or more low priority transactions if the determined danger levels for the two or more threads is high 21 . The processing system of claim 11 , wherein the multithreaded processor is one of a digital signal processor (DSP), general purpose processor (GPP), or a central processing unit (CPU). 22 . The processing system of claim 11 , integrated into a device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer. 23 . A processing system comprising: means for multithreaded processing two or more processing threads; means for determining danger levels for the two or more threads, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource; means for detecting priority levels associated with the two or more threads, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable; and means for scheduling the t

Assignees

Inventors

Classifications

  • in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

  • G06F9/4818Primary

    Priority circuits therefor · CPC title

  • Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

  • by exceeding limits · CPC title

  • G06F9/46Primary

    Multiprogramming arrangements · CPC title

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What does patent US2016350152A1 cover?
Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also …
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification G06F9/4818. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).