Electronic device and power managing method thereof

US2016349831A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016349831-A1
Application numberUS-201615167062-A
CountryUS
Kind codeA1
Filing dateMay 27, 2016
Priority dateMay 28, 2015
Publication dateDec 1, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device includes a battery supplying power to the electronic device, a power management module transferring a first low-voltage interrupt to a processor if a voltage of the battery is lower than or equal to a first voltage, and the processor entering a sleep mode if the first low-voltage interrupt is received from the power management module, wherein the processor ignores other interrupt except an interrupt received from the power management module during the sleep mode. A power managing method of an electronic device, the method comprising generating a first low-voltage interrupt from a power management module if a battery voltage is lower than or equal to a first voltage, entering a sleep mode if the first low-voltage interrupt is generated, and ignoring other interrupts except an interrupt generated from the power management module during the sleep mode.

First claim

Opening claim text (preview).

What is claimed is: 1 . An electronic device comprising: a battery configured to supply power to the electronic device; a power management module configured to transfer a first low-voltage interrupt to a processor if a voltage of the battery is lower than or equal to a first voltage; and the processor configured to enter a sleep mode if the first low-voltage interrupt is received from the power management module, wherein the processor is configured to ignore another interrupt except an interrupt received from the power management module during the sleep mode. 2 . The electronic device of claim 1 , further comprising: a communication module configured to transmit and receive data in connection with a network; and an input module configured to receive a user instruction, wherein the processor is configured to inactivate the communication module and the input module if the first low-voltage interrupt is received from the power management module. 3 . The electronic device of claim 1 , further comprising: a display, wherein the processor is configured to display an object to info′ in entry into the sleep mode on the display if the first low-voltage interrupt is received from the power management module. 4 . The electronic device of claim 1 , wherein the processor is configured to enter the sleep mode after a time since the first low-voltage interrupt is received from the power management module. 5 . The electronic device of claim 1 , wherein the power management module is configured to transfer a second low-voltage interrupt to the processor if the voltage of the battery is lower than or equal to a second voltage that is lower than the first voltage, and wherein the processor is configured to turn off power of the electronic device if the second low-voltage interrupt is received from the power management module. 6 . The electronic device of claim 1 , wherein the power management module is configured to calculate a maximum duration based on battery residual if the voltage of the battery is lower than or equal to the first voltage, and to transfer information of the maximum duration to the processor. 7 . The electronic device of claim 6 , wherein the processor is configured to turn off power of the electronic device after the maximum duration since the entry of the sleep mode. 8 . The electronic device of claim 6 , further comprising: a display, wherein the processor is configured to display an object to inform the maximum duration on the display if the information of the maximum duration is received from the power management module. 9 . The electronic device of claim 1 , wherein the power management module is configured to transfer a charge start interrupt to the processor if the battery begins to be charged, and wherein the processor is configured to enter an awaking mode if the charge start interrupt is received from the power management module during the sleep mode. 10 . The electronic device of claim 9 , further comprising: a display, wherein the processor is configured to display an object to inform the entry of the awaking mode on the display if the awaking mode begins. 11 . A power managing method of an electronic device, the method comprising: generating a first low-voltage interrupt from a power management module if a battery voltage is lower than or equal to a first voltage; entering a sleep mode if the first low-voltage interrupt is generated; and ignoring other interrupts except an interrupt generated from the power management module during the sleep mode. 12 . The power managing method of claim 11 , further comprising: displaying an object to inform entry of the sleep mode on a display if a first low-voltage interrupt is generated from the power management module. 13 . The power managing method of claim 11 , wherein the entering of the sleep mode comprises: entering the sleep mode after a time since a first low-voltage interrupt is generated from the power management module. 14 . The power managing method of claim 11 , further comprising: generating a second low-voltage interrupt from the power management module if the voltage of the battery is lower than or equal to a second voltage that is lower than the first voltage; and turning off power of the electronic device if the second low-voltage interrupt is generated. 15 . The power managing method of claim 11 , further comprising: calculating the maximum duration based on battery residual if the voltage of the battery is lower than or equal to the first voltage. 16 . The power managing method of claim 15 , further comprising: turning off power of the electronic device after the maximum duration since the entry of the sleep mode. 17 . The power managing method of claim 15 , further comprising: displaying an object to inform the maximum duration on a display. 18 . The power managing method of claim 11 , further comprising: generating a charge start interrupt from the power management module if the battery begins to be charged; and entering an awaking mode if the charge start interrupt begins in the sleep mode. 19 . The power managing method of claim 18 , further comprising: displaying an object to inform the entry of an awaking mode on a display if the awaking mode begins. 20 . A computer-readable recording medium recording a program, that when executed, causes an electronic device to perform a method comprising: generating a first low-voltage interrupt from a power management module if a battery voltage is lower than or equal to a first voltage; entering a sleep mode if the first low-voltage interrupt is generated; and ignoring other interrupt except an interrupt that is generated from the power management module during the sleep mode.

Assignees

Inventors

Classifications

  • using interrupt (G06F13/32 takes precedence) · CPC title

  • Power saving in display device · CPC title

  • by lowering the supply or operating voltage · CPC title

  • Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title

  • Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

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What does patent US2016349831A1 cover?
An electronic device includes a battery supplying power to the electronic device, a power management module transferring a first low-voltage interrupt to a processor if a voltage of the battery is lower than or equal to a first voltage, and the processor entering a sleep mode if the first low-voltage interrupt is received from the power management module, wherein the processor ignores other int…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F1/3287. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).