Current-mode bandgap reference with proportional to absolute temperature current and zero temperature coefficient current generation

Patent metadata

Field	Value
Publication number	US-2016349786-A1
Application number	US-201514788529-A
Country	US
Kind code	A1
Filing date	Jun 30, 2015
Priority date	May 29, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

In a current-mode bandgap reference integrated circuit: a bandgap voltage generator is configured to generate a bandgap voltage, a zero-temperature coefficient current generator configured to generate a zero-temperature coefficient current, and a proportional to absolute temperature current generator configured to generate a proportional to absolute temperature current. The integrated circuit includes a first pair of bipolar junction transistors (BJT) comprising a first BJT and a second BJT. The integrated circuit also includes a second pair of bipolar junction transistors, comprising a third BJT and a fourth BJT. The first pair of BJTs matches the second pair of BJTs.

First claim

What is claimed is:

1 . A current-mode bandgap reference integrated circuit comprising:
a bandgap voltage generator configured to generate a bandgap voltage; a zero-temperature coefficient current generator configured to generate a zero-temperature coefficient current; a proportional to absolute temperature current generator configured to generate a proportional to absolute temperature current; a first pair of bipolar junction transistors (BJT) comprising a first BJT and a second BJT; and a second pair of bipolar junction transistors, comprising a third BJT and a fourth BJT, wherein said first pair of BJTs matches said second pair of BJTs.

2 . The current-mode bandgap reference integrated circuit of claim 1 , wherein a ratio of said first BJT pair matches a ratio of said second BJT pair.

3 . The current-mode bandgap reference integrated circuit of claim 1 , further comprising:
a first resistor, wherein a first side of said first resistor is coupled to a collector of said at least one BJT of said first BJT pair, and wherein a second side of said first resistor is coupled to a collector of at least one BJT said second BJT pair.

4 . The current-mode bandgap reference integrated circuit of claim 3 , further comprising:
a plurality of components configured to provide Beta cancellation for said proportional to absolute temperature current.

5 . The current-mode bandgap reference integrated circuit of claim 1 , further comprising:
a first error amplifier, wherein a first input of said first error amplifier is coupled with a collector of at least one BJT of said first BJT pair, and wherein a second input of said error amplifier is coupled through a first resistor to a collector of at least one BJT of said second BJT pair.

6 . The current-mode bandgap reference integrated circuit of claim 1 , further comprising:
a second error amplifier, wherein a first input of said second error amplifier is coupled to a collector of said first BJT, and wherein a second input of said error amplifier is coupled to a collector of said second BJT.

7 . The current-mode bandgap reference integrated circuit of claim 6 , wherein said second error amplifier is configured to drive an n-channel metal oxide semiconductor (NMOS) device, and wherein a source of said NMOS device is coupled to a collector of said second BJT.

8 . The current-mode bandgap reference integrated circuit of claim 6 , wherein said second error amplifier is configured to drive an p-channel metal oxide semiconductor (PMOS) device, and wherein a drain of said PMOS device is coupled to a collector of said second BJT.

9 . The current-mode bandgap reference integrated circuit of claim 6 , further comprising:
a fifth BJT and a sixth BJT, wherein bases of said fifth BJT and said sixth BJT are each coupled to said collector of said second BJT.

10 . The current-mode bandgap reference integrated circuit of claim 9 , further comprising:
four identical n-channel metal oxide semiconductor (NMOS) devices configured as source followers which provide matching voltages at their respective sources, wherein a source of a first of said four NMOS devices is coupled to a collector of said second BJT, a source of a second of said four NMOS devices is coupled to a collector of said fourth BJT, a source of a third of said four NMOS devices is coupled to a collector of said fifth BJT, and a source of a fourth of said four NMOS devices is coupled to a collector of said sixth BJT.

11 . An input device, said input device comprising:
a plurality of sensor electrodes disposed in a sensor electrode pattern; and a processing system coupled with said plurality of sensor electrodes, said processing system configured to:
sense capacitive inputs from said sensor electrodes; and
determine a position of an input object relative to said sensor electrode pattern based on said sensed capacitive inputs; and
a current-mode bandgap reference integrated circuit coupled with said processing system, said integrated circuit comprising:
a bandgap voltage generator configured to generate a bandgap voltage;
a zero-temperature coefficient current generator configured to generate a zero-temperature coefficient current;
a proportional to absolute temperature current generator configured to generate a proportional to absolute temperature current;
a first pair of bipolar junction transistors (BJT) comprising a first BJT and a second BJT; and
a second pair of bipolar junction transistors, comprising a third BJT and a fourth BJT, wherein said first pair of BJTs matches said second pair of BJTs,
wherein said integrated circuit provides one or more of said bandgap voltage, said zero-temperature current, and said proportional to absolute temperature current for use by said processing system.

12 . The input device of claim 11 , wherein a ratio of said first BJT pair matches a ratio of said second BJT pair.

13 . The input device of claim 11 , wherein said integrated circuit further comprises a first resistor, wherein a first side of said first resistor is coupled to a collector of said at least one BJT of said first BJT pair, and wherein a second side of said first resistor is coupled to a collector of at least one BJT said second BJT pair.

14 . The input device of claim 13 , wherein within said integrated circuit:
a first plurality of components are configured to provide Beta cancellation for said first resistor; and a second plurality of components are configured to provide Beta cancellation for said proportional to absolute temperature current.

15 . The input device of claim 11 , wherein said integrated circuit further comprises:
a first error amplifier, wherein a first input of said first error amplifier is coupled with a collector of at least one BJT of said first BJT pair, and wherein a second input of said error amplifier is coupled through a first resistor to a collector of at least one BJT of said second BJT pair.

16 . The input device of claim 11 , said integrated circuit further comprises:
a second error amplifier, wherein a first input of said second error amplifier is coupled to a collector of said first BJT, and wherein a second input of said error amplifier is coupled to a collector of said second BJT.

17 . The current-mode bandgap reference integrated circuit of claim 16 , wherein said second error amplifier is configured to drive an n-channel metal oxide semiconductor (NMOS) device, and wherein a source of said NMOS device is coupled to a collector of said second BJT.

18 . The input device of claim 16 , wherein said second error amplifier is configured to drive an p-channel metal oxide semiconductor (PMOS) device, and wherein a drain of said PMOS device is coupled to a collector of said second BJT.

19 . The input device of claim 16 , wherein said integrated circuit further comprises:
a fifth BJT and a sixth BJT, wherein bases of said fifth BJT and said sixth BJT are each coupled to said collector of said second BJT.

20 . The input device of claim 19 , wherein said integrated circuit further comprises:
four identical n-channel metal oxide semiconductor (NMOS) devices configured as source followers which provide matching voltages at their respective sources, wherein a source of a first of said four NMOS devices is coupled to a collector of said second BJT, a source of a second of said four NMOS devices is coupled to a collector of said fourth BJT, a source of a third of said four NMOS devices is coupled to a collector of said fifth BJT, and a source

Assignees

• Synaptics Inc

Inventors

• Fronczak Kevin
• Bohannon Eric

Classifications

• G05F3/267 Primary

  using both bipolar and field-effect technology · CPC title

• G05F1/567 Primary

  for temperature compensation · CPC title