Regulator with enhanced slew rate

Patent metadata

Field	Value
Publication number	US-2016349777-A1
Application number	US-201615167619-A
Country	US
Kind code	A1
Filing date	May 27, 2016
Priority date	May 28, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

A regulator includes a first operational amplifier configured to receive a reference voltage and a feedback voltage and to output a node voltage based on a difference of the feedback voltage and the reference voltage; a first switch unit configured to receive the node voltage and to supply a recover current based on the node voltage; an output unit configured to output an output voltage and the feedback voltage according to a supply of the recover current; a comparison unit configured to receive the reference voltage and a feedback voltage and to sense a voltage drop of the output voltage; and a second switch unit configured to discharge the first switch unit according to the difference of the reference voltage and the feedback voltage.

First claim

What is claimed is:

1 . A regulator comprising:
a first operational amplifier configured to receive a reference voltage at its inverting input node and a feedback voltage at its non-inverting input node and to output a node voltage based on a difference of the feedback voltage and the reference voltage; a first switch unit configured to receive the node voltage and to supply a recover current based on the node voltage; an output unit configured to output an output voltage and the feedback voltage according to a supply of the recover current; a comparison unit configured to receive the reference voltage at its non-inverting input node and a feedback voltage at its inverting input node and to sense a voltage drop of the output voltage; and a second switch unit configured to discharge the first switch unit according to the difference of the reference voltage and the feedback voltage, wherein the comparison unit comprises: a second operational amplifier configured to receive the reference voltage at its non-inverting input node and the feedback voltage at its inverting input node; and a downshifter configured to downshift an output voltage of the second operational amplifier and to provide the downshifted voltage to the second switch unit.

2 . The regulator of claim 1 , wherein the first switch unit comprises a PMOS transistor coupled with an output node of the first operational amplifier at its gate.

3 . The regulator of claim 2 , wherein the output unit comprises:
a first resistor coupled with a drain of the PMOS transistor at its first node; and a second resistor coupled between a second node of the first transistor and a ground voltage, wherein the output voltage is a voltage at the first node of he first resistor, and the feedback voltage is a voltage is a voltage at the second node of the first resistor.

4 . The regulator of claim 2 , wherein the second switch unit comprises a first NMOS transistor coupled with the gate of the PMOS transistor at its drain and grounded at its source.

5 . The regulator of claim 2 , the gate of the PMOS transistor is discharged according to an output voltage of the comparison unit, and the output voltage of the comparison unit is determined based on the difference of the reference voltage and the feedback voltage.

6 . The regulator of claim 1 , wherein the downshifter is a common-drain amplifier.

7 . The regulator of claim 4 , wherein the downshifter comprises a second NMOS transistor and a variable resistor,
wherein the source of the second NMOS transistor is coupled with one node of the variable resistor, and the other node of the variable resistor is grounded, and wherein the output node of the second operational amplifier is coupled with a gate of the second NMOS transistor, and the node between the second NMOS transistor and the variable resistor is coupled with the gate of the first NMOS transistor.

8 . The regulator of claim 7 ,
wherein the variable resistor comprises a third NMOS transistor, and wherein a gate of the third NMOS transistor is provided with a voltage for biasing the downshifter.

9 . A regulator comprising:
a first operational amplifier suitable for receiving a reference voltage at its inverting input node and a feedback voltage at its non-inverting input node; a PMOS transistor coupled with an output node of the first operational amplifier at its gate; a second operational amplifier for receiving the reference voltage at its non-inverting input node and the feedback voltage at its inverting input node; a first resistor coupled with a drain of the PMOS transistor at its first node; a second resistor coupled with a second node of the first resistor at its first node, and grounded at its second node, wherein the feedback voltage is of the first node of the second resistor; and a first NMOS transistor coupled with the gate of the PMOS transistor at its drain, and grounded at its source, wherein the gate of the PMOS transistor is discharged according to an output voltage of the comparison block, and the output voltage of the comparison block is determined based on difference of the reference voltage and the feedback voltage, and wherein the second operational amplifier provides its output voltage to a gate of the first NMOS transistor.

Assignees

• Sk Hynix Inc

Inventors

• Caracciolo Herve'

Classifications

• G05F1/62

  using bucking or boosting DC sources · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F2203/45248

  the dif amp being designed for improving the slew rate · CPC title

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• G05F1/573 Primary

  with overcurrent detector · CPC title