Dynamic biasing circuits for low drop out (ldo) regulators

Patent metadata

Field	Value
Publication number	US-2016349774-A1
Application number	US-201514930906-A
Country	US
Kind code	A1
Filing date	Nov 3, 2015
Priority date	May 27, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

Dynamic biasing circuits for low drop out (LDO) regulators are described. In some embodiments, an electronic circuit may include a low drop out (LDO) regulator; and a biasing circuit coupled to the LDO regulator, the biasing circuit configured to: monitor a first electrical current and a second electrical current; select a greater of the first or second electrical currents; and provide the selected electrical current to the LDO regulator. In other embodiments, a method may include: providing a digital core and a low drop out (LDO) regulator coupled to the digital core, wherein the digital core is configured to operate in an active mode and in a standby mode; monitoring, via a current selector circuit coupled to the LDO regulator, a first current and a second current; selecting a greater of the first or second electrical currents; and providing the selected current as a biasing current to the LDO regulator.

First claim

1 . An electronic circuit, comprising:
a low drop out (LDO) regulator; and a biasing circuit coupled to the LDO regulator, the biasing circuit configured to:
monitor a first electrical current and a second electrical current;
select a greater of the first or second electrical currents; and
provide the selected electrical current to the LDO regulator.

2 . The electronic circuit of claim 1 , further comprising a digital core coupled to the LDO regulator and configured to receive a regulated supply voltage from the LDO regulator.

3 . The electronic circuit of claim 2 , wherein the digital core is configured to operate in a standby mode and in an active mode.

4 . The electronic circuit of claim 3 , wherein when the digital core is in the standby mode it is configured to operate with the first electrical current, and wherein when the digital core is in the active mode it is configured to operate with the second electrical current.

5 . The electronic circuit of claim 4 , wherein the first electrical current is smaller than the second electrical current.

6 . The electronic circuit of claim 5 , wherein the second electrical current is of the order of 10 μA when the digital core is in the active mode, and approximately 0 A when the digital core is in the standby mode.

7 . The electronic circuit of claim 1 , wherein the biasing circuit includes an current selector circuit configured to receive the first electrical current and the second electrical current.

8 . The electronic circuit of claim 7 , wherein the current selector circuit is further configured to output the greater of the first or second electrical currents as a bias current to the LDO regulator.

9 . The electronic circuit of claim 7 , wherein the current selector circuit is further configured to continuously monitor the first and second electrical currents before and after the digital core transitions between the standby mode and active modes.

10 . The electronic circuit of claim 8 , wherein the current selector circuit further comprises:
a first current mirror configured to receive the first current; a second current mirror coupled to the first current mirror at a difference node and configured to receive the second current; a third current mirror coupled to the difference node and configured to receive a difference current between the first current and the second current; and a fourth current mirror configured to receive the second current and coupled to the third current minor at a summing node that adds the second current to the difference current if the first current is greater than the second current.

11 . An electronic device, comprising:
a digital core; a low drop out (LDO) regulator coupled to the digital core; and a selector circuit coupled to the LDO regulator, the selector circuit configured to:
monitor a first current and a second current;
select a greater of the first or second currents; and
provide the selected current as a biasing current to the LDO regulator.

12 . The electronic device of claim 11 , wherein when the digital core is in a standby mode it is configured to operate with the first current, and wherein when the digital core is in an active mode it is configured to operate with the second current.

13 . The electronic device of claim 12 , wherein the first current is smaller than the second current.

14 . The electronic device of claim 12 , wherein the selector circuit is further configured to continuously monitor the first and second currents before and after the digital core transitions between the standby mode and active modes.

15 . The electronic device of claim 14 , wherein the selector circuit further comprises:
a first current mirror configured to receive the first current; a second current mirror coupled to the first current mirror at a difference node and configured to receive the second current; a third current mirror coupled to the difference node and configured to receive a difference current between the first current and the second current; and a fourth current mirror configured to receive the second current and coupled to the third current minor at a summing node that adds the second current to the difference current if the first current is greater than the second current.

16 . A method, comprising:
providing a digital core and a low drop out (LDO) regulator coupled to the digital core, wherein the digital core is configured to operate in an active mode and in a standby mode; monitoring, via a current selector circuit coupled to the LDO regulator, a first current and a second current; selecting a greater of the first or second electrical currents; and providing the selected current as a biasing current to the LDO regulator.

17 . The method of claim 16 , wherein when the digital core is in the standby mode it operates based on the first current, wherein when the digital core is in the active mode it operates based on the second current.

18 . The method of claim 17 , wherein the first current is smaller than the second current.

19 . The method of claim 18 , wherein monitoring, selecting, and providing operations are performed as the digital core transitions between the standby mode and active modes.

20 . The method of claim 19 , wherein the current selector circuit comprises:
a first current mirror configured to receive the first current; a second current mirror coupled to the first current mirror at a difference node and configured to receive the second current; a third current mirror coupled to the difference node and configured to receive a difference current between the first current and the second current; and a fourth current mirror configured to receive the second current and coupled to the third current minor at a summing node that adds the second current to the difference current if the first current is greater than the second current.

Assignees

• Texas Instruments Inc

Inventors

• Easwaran Sri Navaneethakrishnan
• Devarajan Vijayalakshmi

Classifications

• G05F1/465

  Internal voltage generators for integrated circuits, e.g. step down generators · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title