Hierarchization of cryptographic keys in an electronic circuit

Patent metadata

Field	Value
Publication number	US-2016344548-A1
Application number	US-201414480053-A
Country	US
Kind code	A1
Filing date	Sep 8, 2014
Priority date	Jan 11, 2008
Publication date	Nov 24, 2016
Grant date	—

Abstract

A method of obtaining, in an electronic circuit, at least one first key intended to be used in a cryptographic mechanism, on the basis of at least one second key contained in the same circuit, the first key being stored in at least one first storage element of the circuit, the first storage element being reinitialized automatically after a duration independent of the fact that the circuit is or is not powered. Also described are applications of this method to encrypted transmissions, usage controls, as well as an electronic circuit implementing these methods.

First claim

1 . A method, comprising:
generating, in an electronic circuit, a first key based on a second key; and storing one of the first key and the second key in a first memory of the electronic circuit, the first memory having a memory cell with a storage capacitor and a discharge capacitor and the storing including charging the storage capacitor, wherein the discharge capacitor resets the memory cell after a first threshold period of time has elapsed since the storage capacitor was charged.

2 . The method of claim 1 wherein the first memory has a plurality of memory cells with respective storage capacitors and discharge capacitors, and the storing comprises selectively charging storage capacitors of the plurality of memory cells of the first memory.

3 . The method of claim 1 wherein the storing comprises storing the second key in the first memory.

4 . The method of claim 3 , comprising:
storing the first key in a second memory of the electronic circuit.

5 . The method of claim 4 wherein the second memory has a memory cell with a storage capacitor and a discharge capacitor and the storing the first key in the second memory includes charging the storage capacitor of the memory cell of the second memory, wherein the discharge capacitor of the memory cell of the second memory resets the storage capacitor of the memory cell of the second memory after a second threshold period of time has elapsed since the storage capacitor of the memory cell of the second memory was charged.

6 . The method of claim 5 wherein the second threshold period of time is shorter than the first threshold period of time.

7 . The method of claim 1 wherein the storing comprises storing the first key in the first memory.

8 . The method of claim 1 , comprising limiting a number of uses of the first key within a threshold period of time.

9 . The method of claim 8 wherein limiting the number of uses comprises using a counter having a discharge capacitor which resets the counter after a counter-threshold period of time has elapsed.

10 . The method of claim 1 wherein the second key is stored in a non-volatile memory of the electronic device, the method comprising generating a third key from the first key.

11 . The method of claim 1 , comprising at least one of:
decoding data based on one or more of the first and second keys; encoding data based on one or more of the first and second keys; generating a session key based on one or more of the first and second keys; and controlling a printing process based on one or more of the first and second keys.

12 . A device, comprising:
a plurality of charge-storage memory cells, each charge-storage memory cell including:
a charge-storage capacitor;
read circuitry coupled to the charge-storage capacitor; and
a discharge capacitor coupled to the charge-storage capacitor, which, in operation, resets the memory cell after a threshold period of time has elapsed since the charge-storage capacitor was charged; and
processing circuitry coupled to the plurality of charge-storage memory cells, which, in operation, controls storage of a key in charge-storage memory cells of the plurality of charge-storage memory cells.

13 . The device of claim 12 wherein the charge-storage capacitor has a greater capacitance than the discharge capacitor.

14 . The device of claim 13 wherein the charge-storage capacitor and the discharge capacitor are coupled to a memory-cell node, comprising charging circuitry including a third capacitor coupled to the node, the third capacitor having a capacitance greater than the discharge capacitor.

15 . The device of claim 13 wherein the charge-storage capacitor and the discharge capacitor are coupled to a node and the read circuitry comprises a read transistor coupled to the node.

16 . The device of claim 15 wherein a control gate of the read transistor is coupled to the node.

17 . The device of claim 15 wherein a floating gate of the read transistor is coupled to the node.

18 . The device of claim 17 , comprising charging circuitry including a floating gate MOS transistor having a floating gate coupled to the node.

19 . The device of claim 12 wherein the processing circuitry, in operation, generates a second key from the stored key.

20 . The device of claim 12 comprising a non-volatile memory, wherein the processing circuitry, in operation, generates the stored key from a second key retrieved from the non-volatile memory.

21 . The device of claim 20 wherein the processing circuitry, in operation, generates a third key from the stored key.

22 . The device of claim 12 , comprising a counter having a discharge capacitor, wherein, in operation, the counter counts a number of times the stored key is accessed and the discharge capacitor of the counter resets the counter after a use-threshold period of time has elapsed since the counter was initialized.

23 . The device of claim 12 wherein the charge storage capacitor comprises a floating gate transistor and the discharge capacitor comprises a floating gate transistor.

24 . A system, comprising:
a security device, the security device having:
a plurality of charge-storage memory cells, each charge-storage memory cell including:
a charge-storage capacitor;
read circuitry coupled to the charge-storage capacitor; and
a discharge capacitor coupled to the charge-storage capacitor, which, in operation, resets the memory cell after a threshold period of time has elapsed since the charge-storage capacitor was charged; and

processing circuitry coupled to the plurality of charge-storage memory cells, which, in operation, controls storage of a key in charge-storage memory cells of the plurality of charge-storage memory cells; and
one or more processing devices, which, in operation, couple to the security device.

25 . The system of claim 24 wherein the security device comprises a card.

26 . The system of claim 25 wherein the one or more processing devices comprise a decoder.

27 . The system of claim 25 wherein the card is a payment card and the one or more processing devices comprise a payment card reader.

28 . The system of claim 24 wherein the one or more processing devices comprise a printer.

Assignees

• Proton World Int Nv

Inventors

• Modave Jean-Louis
• Huque Thierry

Classifications

• G06Q20/3552

  Downloading or loading of personalisation data · CPC title

• G06Q20/3829

  involving key management · CPC title

• G06F2221/2137

  Time limited access, e.g. to a computer or data · CPC title

• G06Q20/02

  involving a neutral party, e.g. certification authority, notary or trusted third party [TTP] · CPC title

• H04L2209/24

  Key scheduling, i.e. generating round keys or sub-keys for block encryption · CPC title