Semiconductor device and manufacturing method for the same

Patent metadata

Field	Value
Publication number	US-2016343702-A1
Application number	US-201615145236-A
Country	US
Kind code	A1
Filing date	May 3, 2016
Priority date	May 21, 2015
Publication date	Nov 24, 2016
Grant date	—

Abstract

A semiconductor device is capable of accurately sensing a temperature of a semiconductor element incorporated in a semiconductor substrate. The semiconductor device includes a temperature sensor. The temperature sensor includes a first nitride semiconductor layer of p-type, a first sense electrode, and a second sense electrode. The first sense electrode and the second sense electrode are located to be capable of passing an electric current between the first sense electrode and the second sense electrode through the first nitride semiconductor layer.

First claim

1 . A semiconductor device comprising a temperature sensor, wherein
the temperature sensor comprises: a first nitride semiconductor layer of p-type; and a first sense electrode and a second sense electrode located to be capable of passing an electric current between the first sense electrode and the second sense electrode through the first nitride semiconductor layer.

2 . The semiconductor device of claim 1 further comprising a HEMT,
wherein
the temperature sensor and the HEMT are provided in a common semiconductor substrate,
the HEMT comprises:
a second nitride semiconductor layer,
a third nitride semiconductor layer located on the second nitride semiconductor layer and having a bandgap wider than a bandgap of the second nitride semiconductor layer,
a source electrode electrically connected to the third nitride semiconductor layer,
a drain electrode electrically connected to the third nitride semiconductor layer,
a fourth nitride semiconductor layer of p-type located on the third nitride semiconductor layer and located in a range between the source electrode and the drain electrode in a plan view of an upper surface of the third semiconductor layer, and
a gate electrode located above the fourth nitride semiconductor layer, and
the first nitride semiconductor layer is located on the third nitride semiconductor layer and located outside the range in a plan view of the upper surface of the third semiconductor layer.

3 . The semiconductor device of claim 1 , wherein the first sense electrode and the second sense electrode are located on the first nitride semiconductor layer.

4 . The semiconductor device of claim 3 , wherein the second sense electrode extends on the first nitride semiconductor layer in an annular shape surrounding the first sense electrode.

5 . The semiconductor device of claim 3 , wherein a width of at least a part of the first nitride semiconductor layer positioned between the first sense electrode and the second sense electrode is narrower than a width of the first sense electrode and is narrower than a width of the second sense electrode.

6 . The semiconductor device of claim 2 , wherein
the first sense electrode is located on the first nitride semiconductor layer, and the second sense electrode is located on the third nitride semiconductor layer.

7 . The semiconductor device of claim 2 , wherein a composition of the first nitride semiconductor layer is same as a composition of the fourth nitride semiconductor layer.

8 . The semiconductor device of claim 2 further comprising a Schottky barrier diode,
wherein the Schottky barrier diode comprises:
an anode electrode being in Schottky contact with the third nitride semiconductor layer, and
a cathode electrode being in ohmic contact with the third nitride semiconductor layer.

9 . A method of manufacturing a semiconductor device,
the semiconductor device comprising a HEMT and a temperature sensor provided in a common semiconductor substrate, the method comprising: growing a third nitride semiconductor layer on a second nitride semiconductor layer, the third nitride semiconductor layer having a bandgap wider than a bandgap of the second nitride semiconductor layer, growing a p-type nitride semiconductor layer on the third nitride semiconductor layer, etching a part of the p-type nitride semiconductor layer so as to divide the p-type nitride semiconductor layer into the fourth nitride semiconductor layer and the first nitride semiconductor layer, forming a gate electrode above the fourth nitride semiconductor layer, forming a source electrode and a drain electrode which are electrically connected to the third nitride semiconductor layer so that the fourth nitride semiconductor layer is located in a range between the source electrode and the drain electrode and the first nitride semiconductor layer is located outside the range in a plan view of an upper surface of the third nitride semiconductor layer, and forming a first sense electrode and a second sense electrode so as to be capable of passing an electric current between the first sense electrode and the second sense electrode through the first nitride semiconductor layer.

Assignees

• Toyota Motor Co Ltd

Inventors

• Tomita Hidemoto
• Nagasato Yoshitaka
• Okawa Takashi
• Kanechika Masakazu
• Ueda Hiroyuki

Classifications

• H10P50/646

  of Group III-V materials · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W40/00

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title