Power semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016343644-A1
Application number	US-201415112890-A
Country	US
Kind code	A1
Filing date	May 12, 2014
Priority date	May 12, 2014
Publication date	Nov 24, 2016
Grant date	—

Abstract

A power semiconductor element is fixed on a die pad of the lead frame. A metal plate is bonded to a lower surface of the die pad via an insulating film. The inner lead etc. are disposed in a cavity between a lower mold and an upper mold and are encapsulated with an encapsulation resin. The lower mold has a stepped portion provided in a bottom surface of the cavity below the inner lead. A height of an upper surface of the stepped portion is larger than a height of an upper surface of the power semiconductor element disposed in the cavity. When an encapsulation resin is injected into the cavity, a lower surface of the metal plate is in contact with the bottom surface of the cavity, and the encapsulation resin flows downward from above the stepped portion toward the upper surface of the power semiconductor element.

First claim

1 . A method of manufacturing a power semiconductor device comprising:
preparing a lead frame having an inner lead, an outer lead connected to the inner lead, a die pad disposed at a position lower than that of the inner lead, and a bent portion connecting the inner lead and the die pad; fixing a power semiconductor element on the die pad; bonding a metal plate to a lower surface of the die pad via an insulating film; and encapsulating the inner lead, the die pad, the power semiconductor element, the insulating film and metal plate with an encapsulation resin in a cavity between a lower mold and an upper mold, wherein the lower mold has a stepped portion provided in a bottom surface of the cavity below the inner lead, a height of an upper surface of the stepped portion is larger than a height of an upper surface of the power semiconductor element disposed in the cavity, and when the encapsulation resin is injected into the cavity, a lower surface of the metal plate is in contact with the bottom surface of the cavity, and the encapsulation resin is caused to flow downward from above the stepped portion toward the upper surface of the power semiconductor element.

2 . The method of manufacturing a power semiconductor device of claim 1 , wherein the lower mold includes a projection lower in height than the stepped portion and provided on the bottom surface of the cavity between the stepped portion and the metal plate.

3 . The method of manufacturing a power semiconductor device of claim 1 , wherein the lower mold includes a small stepped portion lower in height than the stepped portion and provided in the bottom surface of the cavity between the stepped portion and the metal plate.

4 . The method of manufacturing a power semiconductor device of claim 1 , wherein the stepped portion is provided along a longer side of the metal plate,
the lower mold includes a projection provided on a bottom surface of the cavity along a shorter side of the metal plate.

5 . The method of manufacturing a power semiconductor device of claim 1 , wherein the stepped portion is provided to surround a periphery of the metal plate.

6 . A power semiconductor device comprising:
a lead frame having an inner lead, an outer lead connected to the inner lead, a die pad disposed at a position lower than that of the inner lead, and a bent portion connecting the inner lead and the die pad; a power semiconductor element fixed on the die pad; a metal plate bonded to a lower surface of the die pad via an insulating film; and an encapsulation resin encapsulating the inner lead, the die pad, the power semiconductor element, the insulating film and metal plate, wherein a lower surface of the metal plate is exposed from a lower surface of the encapsulation resin, a stepped portion is provided in the lower surface of the encapsulation resin below the inner lead, and a height of the lower surface of the encapsulation resin in the stepped portion is larger than a height of an upper surface of the power semiconductor element.

7 . The power semiconductor device of claim 6 , wherein a depression shallower in depth than the stepped portion is provided in a lower surface of the encapsulation resin between the stepped portion and the metal plate.

8 . The power semiconductor device of claim 7 , wherein the depression includes two or more depressions.

9 . The power semiconductor device of claim 6 , wherein a small stepped portion shallower in depth than the stepped portion is provided in a lower surface of the encapsulation resin between the stepped portion and the metal plate.

10 . The power semiconductor device of claim 6 , wherein the stepped portion is provided along a longer side of the metal plate, and
a recess is provided in a lower surface of the encapsulation resin along a shorter side of the metal plate.

11 . The power semiconductor device of claim 6 , wherein the stepped portion is provided to surround a periphery of the metal plate.

Assignees

• Mitsubishi Electric Corp

Inventors

• Kawashima Hiroshi
• Sakamoto Ken
• Shikano Taketoshi

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title